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STM8AF6366TCY Datasheet(PDF) 51 Page - STMicroelectronics |
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STM8AF6366TCY Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 116 page ![]() DocID031156 Rev 1 51/116 STM8AF6388 Memory and register map 114 0x00 7F70 ITC ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F78 to 0x00 7F79 Reserved area (2 bytes) 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00 0x00 7F81 to 0x00 7F8F Reserved area (15 bytes) 0x00 7F90 DM DM_BK1RE DM breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register 0xFF 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) 1. Accessible by debug module only 2. Product dependent value, see Figure 8: Register and memory map. Table 13. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register label Register name Reset status |
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