AT25QL128A datasheet(13/85 Pages) RENESAS

13 / 85 page

DS-AT25QL128A-129 Rev. G

Page 13

Nov 1, 2022

AT25QL128A Datasheet

Device Operation

5.1

Standard SPI Operation

The AT25QL128A features a serial peripheral interface on four signals: Serial Clock (SCK). Chip Select (CS),

Serial Data Input (SI) and Serial Data Output (SO). Standard SPI commands use the SI input pin to serially write

commands, addresses or data to the device on the rising edge of SCK. The SO output pin is used to read data or

status from the device on the falling edge of SCK.

SPI bus operation Modes 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0 and

Mode 3 is the normal state of the SCK signal when the SPI bus master is in standby and data is not being

transferred to the Serial Flash. For Mode 0 the SCK signal is normally low on the falling and rising edges of

CS. For Mode 3 the SCK signal is normally high on the falling and rising edges of CS.

5.2

Dual SPI Operation

The AT25QL128A supports Dual SPI operation. This command allows data to be transferred to, or from, the

device at two times the rate of the standard SPI. The Dual Read command is ideal for quickly downloading code

to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus

(XIP). When using Dual SPI commands the SI and SO pins become bidirectional I/0 pins; IO0 and IO1.

5.3

Quad SPI Operation

The AT25QL128A supports Quad SPI operation. This command allows data to be transferred to, or from, the

device at four times the rate of the standard SPI. The Quad Read command offers a significant improvement

in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from

the SPI bus (XIP). When using Quad SPI command the SI and SO pins become bidirectional IO0 and IO1, and

the WP and HOLD pins become IO2 and IO3 respectively. Quad SPI commands require the non-volatile Quad

Enable bit (QE) in Status Register-2 to be set.

5.4

QPI Operation

The AT25QL128A supports Quad Peripheral Interface (QPI) operation when the device is switched from

Standard/ Dual/ Quad SPI mode to QPI mode using the Enable QPI (38h) command. To enable QPI mode, the

non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI commands, the SI

and SO pins become bidirectional IO0 and IO1, and the WP and HOLD pins become IO2 and IO3, respectively.

The typical SPI protocol requires that the byte-long command code is shifted into the device only through the SI

pin in eight serial clocks. The QPI mode uses all four IO pins to input the command code; thus, only two serial

clocks are required. This can significantly reduce the SPI command overhead and improve system performance

in an XIP environment. Standard / Dual / Quad SPI mode and QPI mode are exclusive. Only one mode can be

active at any given time, the Enable QPI and Disable QPI/ Disable QPI 2 commands are used to switch between

these two modes. Upon power-up, or after software reset using Reset (99h) command, the default state of the

device is Standard / Dual / Quad SPI mode.

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