AT25QL128A datasheet(14/85 Pages) RENESAS

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DS-AT25QL128A-129 Rev. G

Page 14

Nov 1, 2022

AT25QL128A Datasheet

Write Protection

To protect inadvertent writes by noise, several means of protection are applied to the Flash memory.

6.1

Write Protect Features

▪ During power-on reset, all operations are disabled, and no command is recognized.

▪ An internal time delay of tPUW can protect the data against inadvertent changes while the power supply is

outside the operating specification. This includes the Write Enable, Page program, Block Erase, Chip Erase,

Write Security Register, and Write Status Register commands.

▪ For data changes, the Write Enable command must be issued to set the Write Enable Latch (WEL) bit to

0. Power-up, completion of the Write Disable, Write Status Register, Page Program, Block Erase, and Chip

Erase commands are must meet this condition.

▪ Setting the Status Register protect (SRP) and Block protect (SEC, TB, BP2, BP1, and BP0) bits, a portion of

memory can be configured as read only; this is called software protection.

▪ The Write Protect (WP) pin can change the Status Register under hardware control.

▪ The Deep Power-Down mode provides extra protection from unexpected data changes because all commands

are ignored in this mode except for the Release Deep Power-Down command.

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