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70V07 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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70V07 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 20 page  1 JULY 2019 DSC 2943/11 I/O Control Address Decoder MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A14L A0L 2943 drw 01 I/O0L-I/O7L CEL OEL R/ WL SEML I NTL M/ S BUSYR I/O0R-I/O7R A14R A0R SEMR INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER 15 15 R/ WR , 70V07S/L HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 25/35/55ns (max.) – Industrial: 35ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation – IDT70V07S Active: 300mW (typ.) Standby: 3.3mW (typ.) – IDT70V07L Active: 300mW (typ.) Standby: 660 μW (typ.) ◆ ◆ ◆ ◆ ◆ Interrupt Flag ◆ ◆ ◆ ◆ ◆ IDT70V07 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ TTL-compatible, single 3.3V (±0.3V) power supply ◆ ◆ ◆ ◆ ◆ Available in 68-pin PGA and a 80-pin TQFP ◆ Industrial temperature range (-40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information Functional Block Diagram NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. |
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