6.42

70V37L

High-Speed 3.3V 32K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

11

4851 drw 11

tDW

tAPS

ADDR"A"

tWC

DATAOUT "B"

MATCH

tWP

R/

W"A"

DATAIN "A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD

(3)

tWDD

tBAA

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)

Timing Waveform of Write with BUSY (M/S = VIL)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'slave' version.

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL, refer to Truth Table I - Chip Enable.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

4851 drw 12

R/

W"A"

BUSY"B"

tWB

(3)

R/

W"B"

tWH

(1)

(2)

tWP

.