83C451 datasheet(6/22 Pages) PHILIPS

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Philips Semiconductors

Product specification

80C451/83C451/87C451

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, expanded I/O

1998 May 01

I/O Port Structure

The 8XC451 has a total of seven parallel I/O ports. The first four

ports, P0 through P3, are identical in function to those present on

the 80C51 family. The added ports 4 and 5 are identical in function

to port 1; that is, they are standard quasi-bidirectional ports with no

alternate functions and the standard output drive characteristics.

Port 6 is a specialized 8-bit bidirectional I/O port with internal

pullups.

Ports 4 and 5

Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4

is an 8-bit port. Port 4 and port 5 pins with ones written to them, are

pulled high by the internal pull-ups, and in that state can be used as

inputs. Port 4 and 5 are addressed at the special function register

addresses shown in Table 1.

Port 6

Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups

(see Figure 1). This special port can sink/source three LS TTL

inputs and drive CMOS inputs without external pullups. The flexibility

of this port facilitates high-speed parallel data communications. This

port can be used as a standard I/O port, or in strobed modes of

operation in conjunction with four special control lines: ODS, IDS,

AFLAG, and BFLAG. Port 6 operating modes are controlled by the

port 6 control status register (CSR). Port 6 and the CSR are

addressed at the special function register addresses shown in Table

1. The following four control pins are used in conjunction with port 6:

ODS – Output data strobe (Active Low) for port 6. ODS can be

programmed to control the port 6 output drivers and the output

buffer full flag (OBF), or to clear only the OBF flag bit in the CSR

(output-always mode). ODS is active low for output driver control.

the OBF flag can be programmed to be cleared on the negative or

positive edge of ODS.

IDS – Input data strobe (Active Low) for port 6. IDS is used to

control the port 6 input latch and input buffer full flag (IBF) bit in the

CSR. The input data latch can be programmed to be transparent

when IDS is low and latched on the positive transition of IDS, or to

latch only on the positive transition of IDS. Correspondingly, the IBF

flag is set on the negative or positive transition of IDS.

BFLAG – BFLAG is a bidirectional I/O pin which can be

programmed to be an output, set high or low under program control,

or to output the state of the input buffer full flag. BFLAG can also be

programmed to input an enable signal for port 6. When BFLAG is

used as an enable input, port 6 output drivers are in the

high-impedance state, and the input latch does not respond to the

IDS strobe when BFLAG is high. Both features are enabled when

BFLAG is low. This feature facilitates the use of the SC8XC451 in

bused multiprocessor systems.

AFLAG – AFLAG is a bidirectional I/O pin which can be

programmed to be an output set high or low under program control,

or to output the state of the output buffer full flag. AFLAG can also

be programmed to be an input which selects whether the contents of

the output buffer, or the contents of the port 6 control status register

will output on port 6. This feature grants complete port 6 status to

external devices.

Port 6 can be used in a number of different ways to facilitate data

communication. It can be used as a processor bus interface, as a

standard quasi-bidirectional I/O port, or as a parallel printer port

(either polled or interrupt driven).

Processor Bus Interface

Port 6 allows the use of an 8XC451 as an element on a

microprocessor type bus. The host processor could be a general

purpose MPU or the data bus of a microcontroller like the 8XC451

itself. Setting up the 8XC451 as a processor bus interface allows

single or multiple microcontrollers to be used on a bus as flexible

peripheral processing elements. Applications can include: keyboard

scanners, serial I/O controllers, servo controllers, etc.

On reset, port 6 is programmed correctly (that is, Special Function

registers CSR and P6) for use as a bus interface. This prevents the

interface from disrupting data on the bus of a host processor during

power-up.

Standard Quasi-bidirectional I/O Port

To use port 6 as a common I/O port, all of the control pins should be

tied to ground. On hardware reset, bits 2-7 of the CSR are set to

one. With the control pins grounded, the port’s operation and

electrical characteristics will be identical to port 1 on the 80C51. No

further software initialization is required.

Parallel Printer Port

The 8XC451 has the capacity to permit all of the intelligent features

of a common printer to be handled by a single chip. The features of

port 6 allow a parallel port to be designed with only line driving and

receiving chips required as additional hardware. The onboard UART

allows RS232 interfacing with only level shifting chips added. The

8-bit parallel ports 0 to 6 are ample to drive onboard control

functions, even when ports are used for external memory access,

interrupts, and other functions. The RAM addressing ability of ports

0 to 2 can be used to address up to 64k bytes of a hardware

buffer/spooler.

In addition, either end of a parallel interface can be implemented

using port 6, and the interfaces can be interrupt driven or polled in

either case. For more detailed information on port 6 usage, refer to

the application notes entitled “80C451 Operation of Port 6” and

“256k Centronics Printer Buffer Using the SC87C451

Microcontroller.”

CONTROL STATUS REGISTER

The control status register (CSR) establishes the mode of operation

for port 6 and indicates the current status of port 6 I/O registers. All

control status register bits can be read and written by the CPU,

except bits 0 and 1, which are read only. Reset writes ones to bits 2

through 7, and writes zeros to bits 0 and 1 (see Table 3).

CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is

set to a logic 1 when port 6 data is loaded into the input buffer under

control of IDS. This can occur on the negative or positive edge of

IDS, as determined by CSR.2 IBF is cleared when the CPU reads

the input buffer register.

CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag

is set to a logic 1 when the CPU writes to the port 6 output data

buffer. OBF is cleared by the positive or negative edge of ODS, as

determined by CSR.3.

CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high

transition on the IDS pin sets the IBF flag. The Port 6 input buffer is

loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low

transition on the IDS pin sets the IBF flag. Port 6 input buffer is

transparent when IDS is low, and latched when IDS is high.

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