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IDTCSPU877

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIALTEMPERATURERANGE

2006

Integrated Device Technology, Inc.

DSC-5962/38

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IDTCSPU877

COMMERCIAL TEMPERATURE RANGE

1.8V PHASE LOCKED LOOP

DIFFERENTIAL 1:10 SDRAM

CLOCK DRIVER

OCTOBER 2006

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM

NOTE:

The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK.

DESCRIPTION:

The CSPU877 is a PLL based clock driver that acts as a zero delay buffer

to distribute one differential clock input pair(CLK, CLK ) to 10 differential

output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output

(FBOUT,FBOUT). Externalfeedbackpins(FBIN, FBIN)forsynchronization

oftheoutputstotheinputreferenceisprovided.OE,OS,andAVDDcontrolthe

power-down and test mode logic. When AVDD is grounded, the PLL is turned

off and bypassed for test mode purposes. When the differential clock inputs

(CLK,CLK)arebothatlogiclow,thisdevicewillenteralowpower-downmode.

In this mode, the receivers are disabled, the PLL is turned off, and the output

clockdriversaredisabled,resultinginacurrentconsumptiondeviceoflessthan

500

μA.

The CSPU877 requires no external components and has been optimised

forverylowphaseerror,skew,andjitter,whilemaintainingfrequencyandduty

cycle over the operating voltage and temperature range. The CSPU877,

designedforuseinbothmoduleassembliesandsystemmotherboardbased

solutions,providesanoptimumhigh-performanceclocksource.

The CSPU877 is available in Commercial Temperature Range (0°C to

+70°C). See Ordering Information for details.

FEATURES:

• 1 to 10 differential clock distribution

• Optimized for clock distribution in DDR2 (Double Data Rate)

SDRAM applications

• Operating frequency: 125MHz to 340MHz

• Very low skew:

≤≤≤≤≤40ps

• Very low jitter:

≤≤≤≤≤40ps

• 1.8V AVDD and 1.8V VDDQ

• CMOS control signal input

• Test mode enables buffers while disabling PLL

• Low current power-down mode

• Tolerant of Spread Spectrum input clock

• Available in 52-Ball VFBGA and 40-pin VFQFPN packages

APPLICATIONS:

• Meets or exceeds JEDEC standard 82-8 for registered DDR2

clock driver

• Along with SSTU32864/A, DDR2 register, provides complete

solution for DDR2 DIMMs

Y0

Y0

FBOUT

Y1

Y1

Y5

Y5

Y4

Y4

Y3

Y3

Y2

Y2

Y8

Y8

Y6

Y6

Y7

Y7

Y9

Y9

FBOUT

FBIN

FBIN

PLL

CLK

CLK

POWER

DOWN

AND

TEST

MODE

LOGIC

LD

AVDD

OE

OS

LD or OE

LD, OS, or OE

PLL BYPASS

10K

Ω -100KΩ