80C575 datasheet(2/40 Pages) PHILIPS

2 / 40 page

Philips Semiconductors

Product specification

80C575/83C575/

87C575

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

1998 May 01

853-1684 19332

DESCRIPTION

The Philips 80C575/83C575/87C575 is a

high-performance microcontroller fabricated

with Philips high-density CMOS technology.

The Philips CMOS technology combines the

high speed and density characteristics of

HMOS with the low power attributes of

CMOS. Philips epitaxial substrate minimizes

latch-up sensitivity.

The 8XC575 contains an 8k

× 8 ROM

(83C575) EPROM (87C575), a 256

× 8 RAM,

32 I/O lines, three 16-bit counter/timers, a

Programmable Counter Array (PCA), a

seven-source, two-priority level nested

interrupt structure, an enhanced UART, four

analog comparators, power-fail detect and

oscillator fail detect circuits, and on-chip

oscillator and clock circuits.

In addition, the 8XC575 has a low active

reset, and the port pins are reset to a low

level. There is also a fully configurable

watchdog timer, and internal power on clear

circuit. The part includes idle mode and

power-down mode states for reduced power

consumption.

FEATURES

• 80C51 based architecture

– 8k

× 8 ROM (83C575)

– 8k

× 8 EPROM (87C575)

– ROMless (80C575)

– 256

× 8 RAM

– Three 16-bit counter/timers

– Programmable Counter Array

– Enhanced UART

– Boolean processor

– Oscillator fail detect

– Low active reset

– Asynchronous low port reset

– Schmitt trigger inputs

– 4 analog comparators

– Watchdog timer

– Low VCC detect

• Memory addressing capability

– 64k ROM and 64k RAM

• Power control modes:

– Idle mode

– Power-down mode

• CMOS and TTL compatible

• 4.0 to 16MHz

• Extended temperature ranges

• OTP package available

PIN CONFIGURATIONS

CMP0+/P1.0/T2

CMP0-/P1.1/T2EX

ECI/P1.2

CMP0/CEX0/P1.3

CMP1/CEX1/P1.4

CMP2/CEX2/P1.5

CMP3/CEX3/P1.6

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

CMPR-/T0/P3.4

CMP1+/T1/P3.5

CEX4/P1.7

CMP2+/WR/P3.6

CMP3+/RD/P3.7

XTAL2

XTAL1

VSS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

EA/VPP

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

VDD

PQFP

140

DUAL

IN-LINE

PACKAGE

LCC

SU00234

ORDERING INFORMATION

ROMless

ROM

EPROM1

TEMPERATURE RANGE

°C AND PACKAGE

FREQ

(MHz)

DRAWING

NUMBER

P80C575EBP N

P83C575EBP N

P87C575EBPN

OTP

0 to +70, 40-Pin Plastic Dual In-line Package

SOT129-1

P80C575EBA A

P83C575EBA A

P87C575EBAA

OTP

0 to +70, 44-Pin Plastic Leaded Chip Carrier

SOT187-2

P80C575EHAA

P83C575EHAA

P87C575EHAA

OTP

–40 to +125, 44-Pin Plastic Leaded Chip Carrier

SOT187-2

P80C575EBB B

P83C575EBB B

P87C575EBBB

OTP

0 to +70, 44-Pin Plastic Quad Flat Pack

SOT307-2

NOTE:

1. OTP - One Time Programmable EPROM.

80C575 Datasheet(PDF) 2 Page - NXP Semiconductors

80C575 Datasheet(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL