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©2015 Integrated Device Technology, Inc.

Revision B, December 8, 2015

General Description

The 8535-21 is a low skew, high performance 1-to-2

LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The 8535-21 has

two single-ended clock inputs. The single-ended clock input accepts

LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL

levels. The clock enable is internally synchronized to eliminate runt

clock pulses on the output during asynchronous

assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the

8535-21 ideal for those applications demanding well defined

performance and repeatability.

Features

• Two differential 3.3V LVPECL outputs

• Selectable CLK0 or CLK1 inputs for redundant and multiple

frequency fanout applications

• CLK0 or CLK1 can accept the following input levels:

LVCMOS or LVTTL

• Maximum output frequency: 266MHz

• Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels

• Output skew: 20ps (maximum)

• Part-to-part skew: 300ps (maximum)

• Propagation delay: 1.6ns (maximum)

• Additive phase jitter, RMS: 0.03ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

• Available in lead-free (RoHS 6)

Block Diagram

Q0

Q0

Q1

Q1

CLK_EN

CLK_SEL

CLK1

CLK0

D

LE

Q

0

1

Pullup

Pulludown

Pulludown

Pulludown

1

2

3

4

5

6

7

VEE

CLK_EN

CLK_SEL

CLK0

VEE

CLK1

VCC

14

13

12

11

10

9

8

VCC

Q0

Q0

nc

Q1

Q1

VCC

Pin Assignment

8535-21

14 Lead TSSOP

4.40mm x 5.0mm x 0.925mm package body

G Package

Top View

8535-21

Datasheet

Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V

LVPECL CLock Generator