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DA9062 Datasheet(PDF) 90 Page - Renesas Technology Corp |
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DA9062 Datasheet(HTML) 90 Page - Renesas Technology Corp |
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90 / 101 page ![]() DA9062 PMIC for Applications Requiring up to 8.5 A Datasheet Revision 3.8 15-Feb-2022 CFR0011-120-00 90 of 99 © 2022 Renesas Electronics Table 123: VBUCK1_B (0x0B5) Field Bit Type Description BUCK1_SL_B 7:7 R/W This control is only effective when BUCK1_MODE = 0 0: forced to synchronous mode (PWM) when B setting is active. 1: forced to sleep mode (PFM) when B setting is active. VBUCK1_B 6:0 R/W From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV Table 124: VBUCK4_B (0x0B6) Field Bit Type Description BUCK4_SL_B 7:7 R/W This control is only effective when BUCK4_MODE = 0 0: forced to synchronous mode (PWM) when B setting is active. 1: forced to sleep mode (PFM) when B setting is active. VBUCK4_B 6:0 R/W From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV Table 125: VBUCK3_B (0x0B8) Field Bit Type Description BUCK3_SL_B 7:7 R/W This control is only effective when BUCK3_MODE = 0 0: forced to synchronous mode (PWM) when B setting is active. 1: forced to sleep mode (PFM) when B setting is active. VBUCK3_B 6:0 R/W From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV Table 126: VLDO1_B (0x0BA) Field Bit Type Description LDO1_SL_B 7:7 R/W Force LDO sleep mode when B setting is active. Reserved 6:6 R/W Reserved VLDO1_B 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 127: VLDO2_B (0x0BB) Field Bit Type Description LDO2_SL_B 7:7 R/W Force LDO sleep mode if VLDO2_B is selected. Reserved 6:6 R/W Reserved VLDO2_B 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 128: VLDO3_B (0x0BC) Field Bit Type Description LDO3_SL_B 7:7 R/W Force LDO sleep mode if VLDO3_B is selected. Reserved 6:6 R/W Reserved VLDO3_B 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V |
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