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P9027LP-R Datasheet(PDF) 21 Page - Renesas Technology Corp |
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P9027LP-R Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 28 page ![]() P9027LP-R Datasheet © 2016 Integrated Device Technology, Inc 21 April 28, 2016 Byte Address Byte Name Bit Field Typical Default Value Description 0xD9 INTR_MSKD 6 R 0 TS1 voltage is above programmed voltage, INT pin will be toggled. 0xD9 INTR_MSKD 5 R 0 “1” when die temperature is greater than Tdie_shutdown, INT pin will be toggled. 0xD9 INTR_MSKD 4:3 R 0 Reserved 0xD9 INTR_MSKD 2 R 0 “1” when End Of Charge (EOC) pin is set INT ̅̅̅̅̅ pin will be toggled. 0xD9 INTR_MSKD 1 R 0 Reserved 0xD9 INTR_MSKD 0 R 0 “1” when enable ( EN ̅̅̅̅) pin is set high, INT ̅̅̅̅̅ pin will be toggled. Setting 1s in the register enable co-responding fault to send End of Power Transfer. Table 16. Masked Fault Enable Register Byte Address Byte Name Bit Field Typical Default Value Description 0x00 FLT_MSKD_EN 7:5 R/W 0 Reserved. 0x00 FLT_MSKD_EN 4 R/W 0 Thermal regulation loop is fault enabled send End of Power Packet. 0x00 FLT_MSKD_EN 3:0 R/W 1 Reserved. 0x01 FLT_MSKD_EN 7 R/W 1 TS2 fault is enabled to send End of Power Packet. 0x01 FLT_MSKD_EN 6 R/W 1 TS1 fault is enabled to send End of Power Packet. 0x01 FLT_MSKD_EN 5 R/W 1 Die temperature shutdown is enabled to send End of Power Packet. 0x01 FLT_MSKD_EN 4:3 R/W 1 Reserved. 0x01 FLT_MSKD_EN 2 R/W 1 End of Charge is enabled to send End of Power Packet. 0x01 FLT_MSKD_EN 1 R/W 1 Reserved. 0x01 FLT_MSKD_EN 0 R/W 1 Function to use EN pin to send End of Power Transfer is enabled. Setting 1s in the register enable co-responding fault to pull high INT ̅̅̅̅̅ pin. Table 17. Masked Interrupt Enable Byte Address Byte Name Bit Field Typical Default Value Description 0x02 INTR_MSKD_EN 7:5 R/W 1 Reserved. 0x02 INTR_MSKD_EN 4 R/W 1 Thermal regulation interrupt is enabled to toggle INT ̅̅̅̅̅ pin. |
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