CDC9841

PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER

WITH 3-STATE OUTPUTS

SCAS458D – DECEMBER 1994 – REVISED APRIL 1996

6

POST OFFICE BOX 655303

switching characteristics (see Figures 1 and 2)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.135 V

to 3.6 V,

TA = 0°C to 70°C

UNIT

()

()

MIN

MAX

t

†

PCLKn (CL = 20 pF)

200

ps

tskew†

BCLKn (CL = 30 pF)

400

ps

Offset†

PCLKn (CL = 20 pF)

BCLKn (CL = 30 pF)

1

4

ns

Jitt

†

PCLKn (CL = 20 pF)

±250

ps

Jitter

†

BCLKn (CL = 30 pF)

±350

ps

Duty cycle†

Any output

45%

55%

SEL0 = L, SEL1 = L

20

PCLKn (CL = 20 pF)

SEL0 = L, SEL1 = H

16.7

t

SEL0 = H, SEL1 = L

15

ns

tc

SEL0 = L, SEL1 = L

40

ns

BCLKn (CL = 30 pF)

SEL0 = L, SEL1 = H

33.3

SEL0 = H, SEL1 = L

30

t †‡

PCLKn (CL =20 pF) BCLKn (CL =30 pF)

2

ns

tr†‡

PCLKn (CL = 20 pF), BCLKn (CL = 30 pF)

2

ns

tf†‡

PCLKn (CL 20 pF) BCLKn (CL 30 pF)

2

ns

tf†‡

PCLKn (CL = 20 pF), BCLKn (CL = 30 pF)

2

ns

† Specifications are applicable only after the PLL stabilization time has elapsed.

‡ Rise and fall times are characterized using the load circuits shown in Figure 1.