CDC9841

PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER

WITH 3-STATE OUTPUTS

SCAS458D – DECEMBER 1994 – REVISED APRIL 1996

2

POST OFFICE BOX 655303

FUNCTION TABLE

OE

SEL0

SEL1

X1

PCLKn

BCLKn

REFn

CLK24

CLK12

L

X

X

14.31818 MHz

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

H

L

L

14.31818 MHz

50 MHz

25 MHz

14.318 MHz

24 MHz

12 MHz

H

L

H

14.31818 MHz

60 MHz

30 MHz

14.318 MHz

24 MHz

12 MHz

H

H

L

14.31818 MHz

66 MHz

33 MHz

14.318 MHz

24 MHz

12 MHz

H

H

H

TCLK†

TCLK /2

TCLK /4

TCLK

TCLK /4

TCLK /8

† TCLK is a test clock input at the X1 input during test mode.