Philips Semiconductors

Product specification

89C51/89C52/89C54/89C58

80C51 8-bit microcontroller family

4K/8K/16K/32K Flash

1999 Oct 27

17

Interrupt Priority Structure

The 89C51/89C52/89C54/89C58 have a 6-source four-level

interrupt structure.

There are 3 SFRs associated with the four-level interrupt. They are

the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt

Priority High) register makes the four-level interrupt structure

possible. The IPH is located at SFR address B7H. The structure of

the IPH register and a description of its bits is shown in Figure 12.

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

INTERRUPT PRIORITY LEVEL

0

0

Level 0 (lowest priority)

0

1

Level 1

1

0

Level 2

1

1

Level 3 (highest priority)

There are four interrupt levels rather than two as on the 80C51. An

interrupt will be serviced as long as an interrupt of equal or higher

priority is not already being serviced. If an interrupt of equal or

higher level priority is being serviced, the new interrupt will wait until

it is finished before being serviced. If a lower priority level interrupt is

being serviced, it will be stopped and the new interrupt serviced.

When the new interrupt is finished, the lower priority level interrupt

that was stopped will be completed.

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

X0

1

IE0

03H

T0

2

TP0

Y

0BH

X1

3

IE1

N (L)

Y (T)

13H

T1

4

TF1

Y

1BH

SP

5

RI, TI

N

23H

T2

6

TF2, EXF2

N

2BH

NOTES:

1. L = Level activated

2. T = Transition activated

EX0

IE (0A8H)

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables it.

BIT

SYMBOL

FUNCTION

IE.7

EA

Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually

enabled or disabled by setting or clearing its enable bit.

IE.6

—

Not implemented. Reserved for future use.

IE.5

ET2

Timer 2 interrupt enable bit.

IE.4

ES

Serial Port interrupt enable bit.

IE.3

ET1

Timer 1 interrupt enable bit.

IE.2

EX1

External interrupt 1 enable bit.

IE.1

ET0

Timer 0 interrupt enable bit.

IE.0

EX0

External interrupt 0 enable bit.

SU00571

ET0

EX1

ET1

ES

ET2

—

EA

0

1

2

3

4

5

6

7

Figure 10. IE Registers