HSP43168VC-45Z datasheet(13/25 Pages) RENESAS

13 / 25 page

HSP43168

FN2808 Rev 12.00

Page 13 of 25

July 27, 2009

In the Data Flow Diagrams of Figure 10, the order of the data

samples input in to the filter cell is shown by the numbers in

the forward and backward shifting decimation paths. The

output of the filter cell is given by the equation at the bottom

of the block. The diagram in Figure 10A shows data sample

alignment at the pre-adders for the Data/Coefficient

Alignment shown in Figure 9.

This dual filter application is configured by writing 110H to

Address 000H via the microprocessor interface, CIN0-9, A0-8,

and WR. Also, data reversal must be disabled by setting bit 4

of the Control Register at Address 0001H. As in the 8-tap

example, only the unique coefficients need to be stored in the

Coefficient Bank. These coefficients are stored in the first

coefficient set for FIR A by writing C0, C1, C2, and C3 to

Address 100H, 101H, 102H, and 103H respectively. To write

the same filter to the first coefficient set for FIR B, the address

sequence would change to 104H, 105H, 106H, and 107H.

The control signals TXFR, FWRD, RVRS, ACCEN, SHFTEN,

and CSEL0-4 are controlled as described in Example 1.

Example 3: Asymmetric Filter Example

The FIR cells within the HSP43168 can each calculate 4

asymmetric taps on each clock. Thus, a single FIR cell can

implement an 8-tap asymmetric filter if the HSP43168 is

clocked at twice the input data rate. Similarly, if the Dual is

configured as a single filter, a 16-tap asymmetric filter is

realizable. Only one of the two FIR cells are used in this

example for the Block Diagram shown in Figure 11.

For this example, the FIR cells are configured as two 8-tap

asymmetric filters which are clocked at twice the input data

rate. New data is shifted into the forward and backward

decimation paths every other CLK by the assertion of

SHFTEN. The filter output is computed by passing data from

each decimation path to the multipliers on alternating clocks.

Two sets of coefficients are required, one for data on the

forward decimation path, and one for data on the reverse

path. The filter output is generated by accumulating the

multiplier outputs for two CLKs.

The operation of this configuration is better understood by

comparing the Data/Coefficient Alignment in Figure 12 with

the Data Flow Diagrams in Figure 13. The ALUs have been

omitted from the FIR cell diagrams because data is fed to the

multipliers directly from the forward and reverse decimation

paths. The data samples within the FIR cell are shown by the

numbers in the decimation paths.

FIGURE 10C. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED

INTO THE FEED FORWARD STAGE

FIGURE 10. DATA FLOW DIAGRAMS FOR 7-TAP SYMMETRIC

FILTER

C3/2

(X8 + X2)C0 + (X7 + X3)C1 + (X6 + X4)C2 + (X5 + X5)C3/2

HSP43168

INA0-9

INB0-9

OUT9-27

FIR A

FIR B

FIGURE 11. USING HSP43168 AS TWO INDEPENDENT

FILTERS

8-TAP ASYMMETRIC

h(n)

x(n)

FIGURE 12. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP

ASYMMETRIC FILTER

8-TAPS

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