DATASHEET

Low Voltage Zero Delay Buffer

MPC961P

1

©2016 Integrated Device Technology, Inc.

Revision 6, October 4, 2016

OBSOLETE

The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay buffer.

With output frequencies of up to 200 MHz, output skews of 150 ps the device

meets the needs of the most demanding clock tree applications.

Features

•

Fully Integrated PLL

•

Up to 200 MHz I/O Frequency

•

LVCMOS Outputs

•

Outputs Disable in High Impedance

•

LVPECL Reference Clock Options

•

LQFP Packaging

•

32-lead Pb-free Package Available

•

50 ps Cycle-Cycle Jitter

•

150 ps Output Skews

Functional Description

The MPC961 is offered with two different input configurations. The MPC961P

offers an LVCMOS reference clock while the MPC961P offers an LVPECL

reference clock.

When pulled high the OE pin will force all of the outputs (except QFB) into a

high impedance state. Because the OE pin does not affect the QFB output, down

stream clocks can be disabled without the internal PLL losing lock.

The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop

filter components. All control inputs accept

LVCMOS compatible levels and the outputs provide low impedance LVCMOS

outputs capable of driving terminated 50

 transmission lines. For series termi-

nated lines the MPC961 can drive two lines per output giving the device an ef-

fective fanout of 1:36. The device is packaged in a 32 lead LQFP package to

provide the optimum combination of board density and performance.

MPC961P

LOW VOLTAGE

ZERO DELAY BUFFER

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

PCLK

FB_IN

Q0

Q14

QFB

0

PLL

1

F_RANGE

OE

Q1

Q2

Q3

Q15

Q16

Ref

FB

100 – 200 MHz

50 – 100 MHz

The MPC961P requires an external RC filter for the analog power supply pin VCCA. Refer to APPLICATIONS INFORMATION for details.

50 k

50 k

50 k

50 k

PCLK

50 k

50 k

VCC

OBSOLETE