MPC961P Datasheet

2

©2016 Integrated Device Technology, Inc.

Revision 6, October 4, 2016

OBSOLETE

Figure 1. MPC961P Logic Diagram

Figure 2. 32-Lead Pinout (Top View)

Table 1. Pin Configurations

Number

Name

Type

Description

PCLK, PCLK

Input

LVCMOS

PLL reference clock signal

FB_IN

Input

LVCMOS

PLL feedback signal input, connect to a QFB output

F_RANGE

Input

LVCMOS

PLL frequency range select

OE

Input

LVCMOS

Output enable/disable

Q0 – Q16

Output

LVCMOS

Clock outputs

QFB

Output

LVCMOS

PLL feedback signal output, connect to a FB_IN

GND

Supply

Ground

Negative power supply

VCCA

Supply

VCC

PLL positive power supply (analog power supply). The MPC961P requires an

external RC filter for the analog power supply pin VCCA. Please see applications

section for details.

VCC

Supply

VCC

Positive power supply for I/O and core

Table 2. Function Table

Control

Default

0

1

F_RANGE

0

PLL high frequency range. MPC961P input reference and

output clock frequency range is 100 – 200 MHz

PLL low frequency range. MPC961P input reference and

output clock frequency range is 50 – 100 MHz

OE

0

Outputs enabled

Outputs disabled (high-impedance state)

Q5

Q4

Q3

GND

Q2

Q1

Q0

VCC

Q12

Q13

Q14

GND

Q15

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12

3

45

6

78

24

23

22

21

20

19

18

17

16

MPC961P

VCC

Q16

QFB