000-0055321-102

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SLG55321-130010V

Application Example

In a typical application, de-asserting ON (low) turns off the external power N-FET. When the FET is turned off, the voltage at the

load is discharged through a resistor (400 Ohms to 1000 Ohms or Open) internal to the SLG55321 with the discharge current

limited to a maximum of 10mA. When ON is asserted (high), gate voltage is not applied to the gate of the external power N-FET

until after DLY_t then the gate source (Vgs) voltage is ramped up to 11.5 V above the source voltage VS at a slew rate determined

by the internal slew rate control element internal to the SLG55321. Monotonic rise of Vs is maintained even as ID increases

dramatically after the load device turn on threshold voltage is reached. After the source voltage has ramped up to its maximum

steady state value, the Open Drain PG (Power Good) signal is asserted. PG may be used as the ON control of a second

SLG55321 thereby providing power on sequence control of a number of switched power rails, or used in a ‘wired and’ with other

PG signals to indicate all switched power rails are in a power good condition.

The devices will not operate if Vcc is below 3.5 V and will not operate until VD reaches 0.8 V.

The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate

for variations in load current as the voltage is applied.