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SLG55321 Datasheet(PDF) 1 Page - Renesas Technology Corp |
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SLG55321 Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 10 page ![]() ©2022 Renesas Electronics Corporation Rev 1.02 000-0055321-102 Revised February 9, 2022 Triple Rail High Voltage Gate Driver SLG55321-130010V Block Diagram Features • 5 V Power supply • Drain Voltage Range 1.0 V to 20 V • Internal Gate Voltage Charge Pump • Controlled Load Discharge Rate • Controlled Turn on Slew Rate • TDFN-8 Package Application Functions • Power Supply Sequencing with ramp/delay/discharge control • Power Rail “Soft” Switch • Hot Plugging Applications • Low Transient Load Switching • Replace high cost P-channel MOSFETs with lower cost N-channel MOSFETs Pin Configuration Environmental • Pb-Free / RoHS Compliant • Halogen Free Target Application Products • Notebook & Netbook Battery Packs • Notebook & Netbook Sleep Mode Circuits • Server Load Switches • Gaming Sleep Mode Power Switches • Communications Power Switches D S/DIS1 G1/G2/G3 DIS3 GND DIS2 2 3 4 5 6 7 8 ON VCC 1 8-pin TDFN (Top View) VD = 20V Max* Vs G1/G2/G3 S/DIS1 ON GND VCC = 5V D 2 4 6 7 5 1 SLG55321 SLG55320 DIS3 8 DIS2 3 5V 3.3V 1.5V FET1 FET2 FET3 LOAD1 LOAD2 LOAD3 Note: Drain voltage of FET3 cannot exceed 5V due to reliability issue of discharge device The highest VD being switched must be at FET1 and pin 5 of the SLG55321 and SLG55320 1k SLG55321 VG is pumped to VD + 8 V min |
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