MAX22663–MAX22666

Reinforced, Fast, Low-Power,

Six-Channel Digital Isolators

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Analog Devices | 21

Applications Information

Power-Supply Sequencing

The MAX22663-MAX22666 do not require any special power supply sequencing. The logic levels are set independently

on either side by VDDA and VDDB. Each supply can be present over the entire specified range regardless of the level or

presence of the other supply.

Power-Supply Decoupling

To reduce ripple and the chance of introducing data errors, bypass VDDA and VDDB with 0.1μF low-ESR ceramic

capacitors to GNDA and GNDB, respectively. Place the bypass capacitors as close to the power supply input pins as

possible.

Layout Considerations

The PCB designer should follow some critical recommendations in order to get the best performance from the design.

• Keep the input/output traces as short as possible. To keep signal paths low-inductance, avoid using vias.

• Have a solid ground plane underneath the high-speed signal layer.

• Keep the area underneath the devices free from ground and signal planes. Any galvanic or metallic connection

between Side A and Side B defeats the isolation.

Calculating Power Dissipation

The required current for a given supply (VDDA or VDDB) can be estimated by summing the current required for each

channel. The supply current for a channel depends on whether the channel is an input or an output, the channel’s data

rate, and the capacitive or resistive load if it is an output. The typical current for input or output at any data rate can be

estimated from the graphs in Figure 8 and Figure 9. Note that the data in Figure 8 and Figure 9 are extrapolated from the

supply current measurements in a typical operating condition.

The total current for a single channel is the sum of the no-load current (shown in Figure 8 and Figure 9) which is a function

of voltage and data rate, and the load current, which depends on the type of load. Current into a capacitive load is a

function of the load capacitance, the switching frequency, and the supply voltage.

ICL = CL × fSW × VDD

where:

ICL is the current required to drive the capacitive load.

CL is the load capacitance on the isolator’s output pin.

fSW is the switching frequency (bits per second/2).

VDD is the supply voltage on the output side of the isolator.

Current into a resistive load depends on the load resistance, the supply voltage, and the average duty cycle of the data

waveform. The DC load current can be conservatively estimated by assuming the output is always high.

IRL = VDD ÷ RL

where:

IRL is the current required to drive the resistive load.

VDD is the supply voltage on the output side of the isolator.

RL is the load resistance on the isolator’s output pin.

Example (See Figure 10): A MAX22664C is operating with VDDA = 2.5V, VDDB = 3.3V, channel 1 operating at 20Mbps

with a 15kΩ resistive load; channel 2 operating at 100Mbps with a 10pF capacitive load; channel 3 is not in use and the

resistive load is negligible since the isolator is driving a CMOS input; channel 4 held high with a 10kΩ resistive load;

channel 5 operating at 50Mbps with a 20kΩ resistive load; and channel 6 operating at 200Mbps with a 15pF capacitive

load. Refer to Table 4 and Table 5 for VDDA and VDDB supply current calculation worksheets.