FN7631 Rev.4.00

Page 13 of 27

Sep 7, 2017

ISL97671

The ISL97671 allows the user to program the amount of phase

shift degree in 7-bit resolution, as shown in Figure 24. To enable

programmable phase shifting, the user must write to the Phase

Shift Control register with EqualPhase = 0 and the desirable

phase shift value of PhaseShift[6:0]. The delay between CH5 and

the repeated CH0 is the rest of the PWM cycle.

Switching Frequency

The default switching frequency is 600kHz but it can be selected

to 600kHz or 1.2MHz if the SMBus/I2C communications is used.

The switching frequency select bit is accessible in the SMBus/I2C

Configuration Register 0x08 bit 2.

5V Low Dropout Regulator

A 5V LDO regulator is present at the VDC pin to develop the

necessary low voltage supply, which is used by the chips internal

control circuitry. Because VDC is an LDO pin, it requires a bypass

capacitor of 1µF or more for the regulation. Low input voltage also

allows only lower output voltage applications only with the

maximum boost ratio defined in “Components Selections” on

page 24. The VDC pin can be used as a coarse reference with a few

mA sourcing capability.

In-rush Control and Soft-start

The ISL97671 has separately built in independent in-rush control and

soft-start functions. The in-rush control function is built around the

short circuit protection FET, and is only available in applications, which

include this device. At start-up, the fault protection FET is turned on

slowly due to a 30µA pull-down current output from the FAULT pin.

This discharges the fault FET's gate-source capacitance, turning on

the FET in a controlled fashion. As this happens, the output capacitor

is charged slowly through the weakly turned on FET before it becomes

fully enhanced. This results in a low in-rush current. This current can

be further reduced by adding a capacitor (in the 1nF to 5nF range)

across the gate-source terminals of the FET.

Once the chip detects that the fault protection FET is turned on

hard, it is assumed that in-rush has completed. At this point, the

boost regulator will begin to switch and the current in the

inductor will ramp-up. The current in the boost power switch is

monitored and the switching is terminated in any cycle where the

current exceeds the current limit. The ISL97671 includes a soft-

start feature where this current limit starts at a low value

(275mA). This is stepped up to the final 2.2A current limit in 7

further steps of 275mA. These steps will happen over at least

8ms, and will be extended at low LED PWM frequencies if the

LED duty cycle is low. This allows the output capacitor to be

charged to the required value at a low current limit and prevents

high input current for systems that have only a low to medium

output current requirement.

For systems with no master fault protection FET, the in-rush

current will flow towards COUT when VIN is applied and it is

determined by the ramp rate of VIN and the values of COUT and L.

Fault Protection and Monitoring

The ISL97671 features extensive protection functions to cover all

the perceivable failure conditions. The failure mode of a LED can

be either open circuit or as a short. The behavior of an open

circuited LED can additionally take the form of either infinite

resistance or, for some LEDs, a zener diode, which is integrated

into the device in parallel with the now opened LED.

For basic LEDs (which do not have built-in zener diodes), an open

circuit failure of an LED will only result in the loss of one channel

of LEDs without affecting other channels. Similarly, a short circuit

condition on a channel that results in that channel being turned

off does not affect other channels unless a similar fault is

FIGURE 22. 6 EQUAL PHASE CHANNELS PHASE SHIFT

ILLUSTRATION

ILED0

ILED1

ILED2

ILED3

ILED4

ILED5

ILED0

tON

tOFF

PWMI

60%

40%

tFPWM

60%

40%

tD1

tD1

tD1

tD1

tD1

tD2

FIGURE 23. 4 EQUAL PHASE CHANNELS PHASE SHIFT

ILLUSTRATION

ILED1

ILED2

ILED3

ILED4

ILED1

tON

tOFF

PWMI

60%

40%

60%

40%

tD1

t

D1

t

D1

t

D2

tFPWM

(t

PWMout)

tPWMin

tD1 = Fixed Delay with Integer only while the decimal value will be discarded (eg. 63.75=63)

FIGURE 24. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY

ILED0

ILED1

ILED2

ILED3

ILED4

ILED5

tPD

tPD

tPD

tPD

tPD

tON

tOFF

tFPWM