Quad LVDS Line Driver with High-ESD

Tolerance and Flow-Through Pinout

6

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Pin Description

PIN

TSSOP

QFN

NAME

FUNCTION

115

EN

LVTTL/LVCMOS Enable Input. All outputs are disabled when EN is low. Internally

pulled down.

2

16

IN1

LVTTL/LVCMOS Input 1. Input internally pulled down.

3

1

IN2

LVTTL/LVCMOS Input 2. Input internally pulled down.

42

5

3

GND

Ground

6

4

IN3

LVTTL/LVCMOS Input 3. Input internally pulled down.

7

5

IN4

LVTTL/LVCMOS input 4. Input internally pulled down.

86

EN

LVTTL/LVCMOS Inverting Enable Input. All outputs are disabled when EN is high.

Internally pulled down.

9

7

OUT4-

Inverting LVDS Output 4

10

8

OUT4+

Noninverting LVDS Output 4

11

9

OUT3+

Noninverting LVDS Output 3

12

10

OUT3-

Inverting LVDS Output 3

13

11

OUT2-

Inverting LVDS Output 2

14

12

OUT2+

Noninverting LVDS Output 2

15

13

OUT1+

Noninverting LVDS Output 1

16

14

OUT1-

Inverting LVDS Output 1

—

EP

Exposed Pad

Exposed Pad. Solder to ground plane.

Typical Operating Characteristics (continued)

300

350

450

400

500

550

TRANSITION TIME

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

3.0

3.2

3.3

3.1

3.4

3.5

3.6

FREQUENCY = 200MHz

300

350

450

400

500

-40

10

-15

35

60

85

TRANSITION TIME

vs. AMBIENT TEMPERATURE

TEMPERATURE (

°C)

FREQUENCY = 200MHz