MPC106 Part Number Specifications

3

Ordering Information

1.10 Ordering Information

The following table provides the ordering information for the extended temperature MPC106 part numbers

described herein.

1001

3:1

x4

—

60 (240)

75 (300)

—

0011

PLL-bypass 3

PLL off

SYSCLK clocks core circuitry directly

1x core/SYSCLK ratio implied

1111

Clock off 4

PLL off

no core clocking occurs

Notes:

1 PLL[0–3] settings not listed are reserved. Some PLL configurations may select bus, CPU, or VCO frequencies

which are not useful, not supported, or not tested. See Section 1.4.2.1, “Clock AC Specifications,” for valid

SYSCLK and VCO frequencies.

2 5:2 clock modes are only supported by MPC106 Rev 4.0; earlier revisions do not support 5:2 clock modes.

The 5:2 modes require a 60x bus clock applied to the 60x clock phase (LBCLAIM) configuration input signal

during power-on reset, hard reset, and coming out of sleep and suspend power-saving modes.

3 In PLL-bypass mode, the SYSCLK input signal clocks the internal circuitry directly, the PLL is disabled, and

the core/SYSCLK ratio is set for 1:1 mode operation. This mode is intended for factory use and third-party tool

vendors only. Note also: The AC timing specifications given in this document do not apply in PLL-bypass

mode.

4 In clock-off mode, no clocking occurs inside the MPC106 regardless of the SYSCLK input.

Table 12. Ordering Information for the PowerPC 106

Package

Type

Device

Rev

Process

CPU

Frequency

(MHz)

Motorola

Part Number

304

CBGAP

4.0

PPC1.4

66, 83

MPC106ARXTG

Table 11. PLL Configuration (Continued)

PLL[0–3]1

Core/SYSCL

K Ratio

VCO

Multiplier

Core Frequency (VCO Frequency) in MHz

PCI Bus

16.6 MHz

PCI Bus

20 MHz

PCI Bus

25 MHz

PCI Bus

33.3 MHz