ADAV400

Rev. 0 | Page 9 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

2

VREF

3

AGND

4

AVDD1

7

NC

6

NC

5

NC

1

FILTA

8

NC

9

NC

10

NC

12

NC

13

DGND

14

DVDD

15

AD0

16

SDA

17

SCL

18

TEST0

19

TEST1

20

DGND

11

NC

59

58

57

54

55

56

60

53

52

VOUT2

VOUT1

AUXR1

HPOUTR

AVDD3

AUXL1

VOUT3

HPOUTL

AGND

51

AGND

49

AVDD2

48

DGND

47

DVDD

46

RESET

45

NC

44

NC

43

SDO3

42

SDO2

41

DGND

50

PLL_LF

NC = NO CONNECT

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PIN 1

ADAV400

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

I/O

Description

1

FILTA

O

ADC Filter Decoupling Node for the ADC. Decouple this pin to AGND (Pin 3).

2

VREF

Voltage Reference. This pin is driven by an internal 1.5 V reference voltage. Decouple this pin to AGND

(Pin 3)

3

AGND

ADC Ground. Connect this pin to the analog ground plane.

4

AVDD1

Analog Power Supply Pin for the ADC. Connect this pin to 3.3 V and decouple to AGND (Pin 3)

5 to 12,

65, 66

NC

Not Connected Internally.

13, 20,

28, 32,

41, 48

DGND

Digital Ground. Connect this pin to the digital ground plane.

14, 21,

31, 40,

47

DVDD

Digital Power Supply Pins. Connect these pins to 1.8 V, either directly or by using the on-chip regulator.

Decouple to DGND

15

AD0

I

and 0x2B (read)

16

SDA

I/O

17

SCL

I

18

TEST0

Test Pin. Connect to ODVDD.

19

TEST1

Test Pin. Connect to ODVDD.

22 to 25

SDIN [0:3]

I

Serial Data Inputs. BCLK1 and LRCLK1 are used as the timing signals for SDIN0 to SDIN3.

26

LRCLK0

I

Left/Right Clock for Sample Rate Converter (SRC). This input frame synchronization signal is associated

with SDIN0 to SDIN3 when one of these input channels is redirected to the SRC.

27

BCLK0

I

Bit Clock for Sample Rate Converter (SRC). This input clock is associated with SDIN0 to SDIN3 when one of

these input channels is redirected to the SRC.

29

ODVDD

Digital Interface Supply (3.3 V) Pin. Connect this pin to a 3.3 V digital supply. Decouple to DGND.

30

VDRIVE

Drive for External PNP Transistor. This is used with the on-chip 1.8 V regulator circuit