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ADAV400

Rev. 0 | Page 26 of 36

SERIAL DATA INPUT/OUTPUT PORTS

The flexible serial data input/output ports of the ADAV400

can be set to accept or transmit data in 2-channel format or in

an 8- or 16-channel TDM stream. Data is processed in twos

complement, MSB-first format. The left channel data field

always precedes the right channel data field in the 2-channel

streams. In the TDM modes, Slot 0 to Slot 3 (8-channel TDM)

or Slot 0 to Slot 7 (16-channel TDM) fall in the first half of the

audio frame, and Slot 4 to Slot 7 (or Slot 8 to Slot 15 in 16-channel

TDM) are in the second half of the frame. The serial modes are

set in the serial input and output control registers.

The input and output control register define the operation of

the serial ports. Because BCLK1 and LRCLK1 are used for both

input and output serial port timing, some care must be taken

when individually programming serial modes. For example,

programming the input serial port to TDM and the output port

to left-justified is not a valid state.

In TDM mode, there are some restrictions to ADAV400 operation,

which are outlined in Table 26. There are two modes of operation.

In both 8-channel and 16-channel TDM modes, SDIN0 is the

input for the TDM stream and SDO0 is the output.

Figure 34 shows the ADAV400 operating in TDM mode. Refer

to the Serial Data Input/Output Ports section for a more

complete description of the modes of operation.

Note that in 16-channel TDM mode, the ADC and DACs are no

longer used because all 16 input and output channels have been

redirected to the serial input and output ports.

Table 26. Serial Output Port Master/Slave Mode Capabilities

2-Channel Modes (I2S, Left-Justified, Right-Justified)

8-Channel TDM

16-Channel TDM

48 kHz

Master and slave

Slave only

96 kHz

Master and slave

Slave only

192 kHz

Master and slave

Slave only

Table 27. Data Format Configurations

Format

LRCLK Polarity

LRCLK

Type

BCLK Polarity

MSB Position

I2S (Figure 31)

Frame begins on

falling edge

Clock

Data changes on

falling edge

Delayed from LRCLK edge by one BCLK

Left-Justified (Figure 32)

Frame begins on

rising edge

Clock

Data changes on

falling edge

Aligned with LRCLK edge

Right-Justified (Figure 33)

Frame begins on

rising edge

Clock

Data changes on

falling edge

Delayed from LRCLK edge by 8, 12, or 16 BCLKs

TDM with Clock (Figure 34)

Frame begins on

falling edge

Clock

Data changes on

falling edge

Delayed from start of word clock by one BCLK

TDM with Pulse (Figure 35)

Frame begins on

rising edge

Pulse

Data changes on

falling edge

Delayed from start of word clock by one BCLK

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