MC56F8023E

Rev. 0, 09/2006

56F8023

Freescale Semiconductor

©Freescale Semiconductor, Inc. 2006. All rights reserved.

Preliminary Chip Errata

56F8023 Digital Signal Controller

This document reports errata information on chip revision A. Errata numbers are in the form n.m, where n is the

number of the errata item and m identifies the document revision number. This document is a pre-publication draft.

Chip Revision A Errata Information:

The following errata items apply only to Revision A 56F8023 devices.

Errata

Number

Description

Impact and Work Around

1.0

In the DAC, the up/down

counter which implements

waveform generation in

automatic mode in the DAC

gasket does not handle negative

numbers.

Impact:

Down counting to a negative number will wrap the counter and continue down

counting.

Work Around:

Adjust MAXVAL, MINVAL, and/or STEP size so the terminal value while down

counting is positive or zero.

2.0

when the loss occurs while the

ACK bit of data bytes is received

in master RX mode.

Impact:

No impact on bus behavior.

Arbitration loss software counters will not be accurate in this situation.

Work Around:

None available.

3.0

flushes don’t interrupt the CPU.

Impact:

If the number of bytes written to the TX FIFO exceeds the number of data bytes

retrieved by the remote master, there is no CPU indication that the excess data bytes

were flushed from the TX FIFO.

Software must accommodate this behavior

Work Around:

None available

4.0

data during general calls when

both master and slave are

enabled and the module initiates

the general call. This means the

transmission will always be

completed and it’s impossible to

determine if another device is

ACKing the call.

Impact:

Since the module always ACKs the general call address and data in the scenario, the

module will never know if any of the other nodes NACKed the general call.

Use work around until fixed.

Work Around:

Disable slave mode prior to initiating a general call.