56F8023 datasheet(2/4 Pages) FREESCALE

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56F8023 Preliminary Technical Data

5.0

Although required by the Philips

spec, the I2C does not reset its

bus logic, and thereby prepare to

receive address following an

unexpected START or repeated

START. An unexpected START

or repeated START is one that is

not positioned according to the

proper format.

Impact:

Avoid all unexpected START conditions. Typically, this is not an issue in a single

master system. In a multi-master system, avoid an unexpected START by powering

up all master I2Cs while the bus remains idle or by initiating master activity in a newly

powered up master only when the bus is idle.

Work Around:

Use work around until fixed.

6.0

The I2C bus locks up when

disabled in slave TX mode.

Impact:

Same as description.

Work Around:

The user’s software must ensure that slv_activity and mst_activity are deasserted when

disabling the module. To prevent this problem, follow the full module disabling

procedure outlined in documentation.

7.0

If you power up the I2C in

master mode and write to the TX

FIFO for the first time while the

bus is not idle, the I2C may

transmit onto the non-idle bus.

Impact:

Same as description.

Work Around:

If it’s possible to power up the module while the bus is busy, the user should monitor

for I2C bus STOP detection or idle conditions before writing to the TX FIFO for the

first time.

8.0

I2C may deassert interrupts

during module disabling.

Impact:

Same as description; reported to inform user of related module functionality.

Work Around:

Once enabled, if I2C is disabled, the user’s software must be able to manage the

possible deassertion of asserted interrupt outputs.

9.0

I2C prematurely releases SCL in

slave TX abort, causing all-ones

data to be clocked out.

Impact:

Same as description.

Work Around:

While operating in slave transmitter mode, do not write a read command to the TX

FIFO .

10.0

I2C provides only one IPBus

clock period of noise

suppression.

Impact:

Same as description.

Work Around:

Ensure that noise spikes do not exceed one IPBus clock period.

Chip Revision A Errata Information:

The following errata items apply only to Revision A 56F8023 devices.

Errata

Number

Description

Impact and Work Around

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