Inductor Selector for V

20174737

C

noise filtering and stability, but also prevents false triggering

of the V

this reason, C

stability, and should be a good quality, low ESR, ceramic

capacitor.

C

Experimentation is usually necessary to determine the mini-

mum value for C

larger value. A load which creates significant transients re-

quires a larger value for C

C

high frequency noise at V

located close to the LM3100.

C

current during the on-time, and limit the voltage ripple at V

on the assumption that the voltage source feeding V

an output impedance greater than zero. If the source’s dy-

namic impedance is high (effectively a current source), it

supplies the average input current, but not the ripple current.

At maximum load current, when the buck switch turns on, the

current into V

inductor’s ripple current, ramps up to the peak value, then

drop to zero at turn-off. The average current during the

on-time is the load current. For a worst case calculation, C

IN

must supply this average load current during the maximum

on-time. C

(8)

where I

and

∆V is the allowable ripple voltage at V

C

long lead inductance at V

capacitor is recommended, located close to the LM3100.

C

quality ceramic capacitor with low ESR is recommended as

C

at turn-on. A low ESR also helps ensure a complete recharge

during each off-time.

C

time, i.e. the time for the reference voltage at the regulation

comparator, and the output voltage, to reach their final value.

The time is determined from the following:

C

is needed for Discontinuous Conduction Mode to improve

the output ripple performance, the recommended value for

C

PC BOARD LAYOUT

The LM3100 regulation, over-voltage, and current limit com-

parators are very fast, and will respond to short duration

noise pulses. Layout considerations are therefore critical for

optimum performance. The layout must be as neat and

compact as possible, and all of the components must be as

close as possible to their associated pins. Refer to the

functional block diagram, the loop formed by C

and low-side switches internal to the IC, and the PGND pin

should be as small as possible. The PGND connection to Cin

should be as short and direct as possible. There should be

several vias connecting the Cin ground terminal to the

ground plane placed as close to the capacitor as possible.

The boost capacitor should be connected as close to the SW

and BST pins as possible. The feedback divider resistors

and the C

A long trace run from the top of the divider to the output is

generally acceptable since this is a low impedance node.

Ground the bottom of the divider directly to the GND (pin 7).

The output capacitor, C

the load and tied directly into the ground plane. The inductor

should connect close to the SW pin with as short a trace as

possible to help reduce the potential for EMI (electro-

magnetic interference) generation.

If it is expected that the internal dissipation of the LM3100

will produce excessive junction temperatures during normal

operation, good use of the PC board’s ground plane can help

considerably to dissipate heat. The exposed pad on the

bottom of the IC package can be soldered to a ground plane

and that plane should extend out from beneath the IC to help

dissipate the heat. The exposed pad is internally connected

to the IC substrate. Additionally the use of wide PC board

traces, where possible, can help conduct heat away from the

IC. Using numerous vias to connect the die attach pad to an

internal ground plane is a good practice. Judicious position-

ing of the PC board within the end product, along with the

use of any available air flow (forced or natural convection)

can help reduce the junction temperature.

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