AD9755AST datasheet(18/28 Pages) AD

18 / 28 page

REV. B

AD9755

–18–

POWER AND GROUNDING CONSIDERATIONS, POWER

SUPPLY REJECTION

Many applications seek high speed and high performance under

less than ideal operating conditions. In these applications, the

implementation and construction of the printed circuit board is

as important as the circuit design. Proper RF techniques must

be used for device selection, placement, and routing, as well as

power supply bypassing and grounding to ensure optimum

performance. Figures 34 to 41 illustrate the recommended

printed circuit board ground, power, and signal plane layouts

that are implemented on the AD9755 evaluation board.

One factor that can measurably affect system performance is the

ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution.

This is referred to as the Power Supply Rejection Ratio. For dc

variations of the power supply, the resulting performance of the

DAC directly corresponds to a gain error associated with the

DAC’s full-scale current, IOUTFS. AC noise on the dc supplies is

common in applications where the power distribution is generated

by a switching power supply. Typically, switching power supply

noise occurs over the spectrum from tens of kHz to several MHz.

The PSRR versus frequency of the AD9755 AVDD su

pply over

this frequency range is shown in Figure 25.

FREQUENCY (MHz)

Figure 25. Power Supply Rejection Ratio

Note that the units in Figure 25 are given in units of (amps out/

volts in). Noise on the analog power supply has the effect of

modulating the internal switches, and therefore the output current.

The voltage noise on AVDD thus is added in a nonlinear manner

to the desired IOUT. Due to the relative different size of these

switches, PSRR is very code-dependent. This can produce a

mixing effect that can modulate low frequency power supply

noise to higher frequencies. Worst-case PSRR for either one of

the differential DAC outputs occurs when the full-scale current is

directed toward that output. As a result, the PSRR measurement

in Figure 25 represents a worst-case condition in which the

digital inputs remain static and the full-scale output current of

20 mA is directed to the DAC output being measured.

An example serves to illustrate the effect of supply noise on the

analog supply. Suppose a switching regulator with a switching

frequency of 250 kHz produces 10 mV rms of noise and, for

simplicity sake (i.e., ignore harmonics), all of this noise is con-

centrated at 250 kHz. To calculate how much of this undesired

noise will appear as current noise superimposed on the DAC’s

full-scale current, IOUTFS, one must determine the PSRR in dB

using Figure 25 at 250 kHz. To calculate the PSRR for a given

RLOAD, such that the units of PSRR are converted from A/V to

V/V, adjust the curve in Figure 25 by the scaling factor 20

× Log

(RLOAD). For instance, if RLOAD is 50

Ω, the PSRR is reduced by

34 dB, i.e., PSRR of the DAC at 250 kHz, which is 85 dB in

Figure 25, becomes 51 dB VOUT/VIN.

Proper grounding and decoupling should be a primary objective

in any high speed, high resolution system. The AD9755 features

separate analog and digital supply and ground pins to optimize

the management of analog and digital ground currents in a system.

In general, AVDD, the analog supply, should be decoupled to

ACOM, the analog common, as close to the chip as physically

possible. Similarly, DVDD, the digital supply, should be decoupled

to DCOM as close to the chip as physically possible.

For those applications that require a single 3.3 V supply for both

the analog and digital supplies, a clean analog supply may be

generated using the circuit shown in Figure 26. The circuit

consists of a differential LC filter with separate power supply and

return lines. Lower noise can be attained by using low ESR type

electrolytic and tantalum capacitors.

AVDD

ACOM

100 F

ELECT.

10 F-22 F

TANT.

0.1 F

CER.

TTL/CMOS

LOGIC

CIRCUITS

3.3V

POWER SUPPLY

FERRITE

BEADS

Figure 26. Differential LC Filter for a Single 3.3 V Application

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