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DP83251V Datasheet(PDF) 39 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83251V
Description  PLAYER Device (FDDI Physical Layer Controller)
PDF  96 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83251V Datasheet(HTML) 39 Page - National Semiconductor (TI)

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50 Registers (Continued)
NOISE PRESCALE THRESHOLD REGISTER (NPTR)
The Noise Prescale Threshold Register contains the start value for the Noise Prescale Counter The Noise Prescale Counter is a
count-down counter and it is used in conjunction with the Noise Counter for counting the Noise events The Noise Prescale
Counter decrements once every 80 ns while there is a noise event When the Noise Prescale Counter reaches zero it reloads
the count with the content of the Noise Prescale Threshold Register and also causes the Noise Counter to decrement
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true
(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State Active
Line State or Line State Unknown
or
(2) The current Line State is either Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect
or
(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle
In addition the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero
The Noise Counter and Noise Prescale Counter will continue to count without resetting or reloading the threshold values if a
Line State change occurs and the new line state is either Noise Line State Active Line State or Line State Unknown
When both the Noise Threshold Counter and Noise Counter both reach zero the Noise Threshold bit of the Receive Condition
Register A will be set
ACCESS RULES
ADDRESS
READ
WRITE
0Eh
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
NPT7
NPT6
NPT5
NPT4
NPT3
NPT2
NPT1
NPT0
Bit
Symbol
Description
D0
NPT0
NOISE PRESCALE THRESHOLD BIT k0l
Least significant bit (LSB) of the
start value of the Noise Prescale Counter
D1–6
NPT1–6
NOISE PRESCALE THRESHOLD BITk1–6l
Intermediate bits of start
value for the Noise Prescale Counter
D7
NPT7
NOISE PRESCALE THRESHOLD BIT k7l
Most significant bit (MSB) of the
start value for the Noise Prescale Counter
39



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