ICS9LP525-2

IDT® PC MAIN CLOCK

1397—11/08/10

56-pin CK505 for Intel Desktop Systems

1

DATASHEET

Pin Configuration

Recommended Application:

CK505 clock, 56-pin Intel Yellow Cover part

Output Features:

•

2 - CPU differential low power push-pull pairs

•

7- SRC differential low power push-pull pairs

•

1 - CPU/SRC selectable differential low power push-pull pair

•

1 - SRC/DOT selectable differential low power push-pull pair

•

5 - PCI, 33MHz

•

1 - PCI_F, 33MHz free running

•

1 - USB, 48MHz

•

1 - REF, 14.318MHz

Key Specifications:

•

CPU outputs cycle-cycle jitter < 85ps

•

SRC output cycle-cycle jitter < 125ps

•

PCI outputs cycle-cycle jitter < 250ps

•

+/- 100ppm frequency accuracy on all outputs

•

SRC are PCIe Gen2 compliant

PCI0/CR#_A 1

56 SCLK

VDDPCI 2

55 SDATA

PCI1/CR#_B 3

54 REF0/FSLC/TEST_SEL

PCI2/TME 4

53 VDDREF

PCI3/CFG0 5

52 X1

PCI4/SRC5_EN 6

51 X2

PCI_F5/ITP_EN 7

50 GNDREF

GNDPCI 8

49 FSLB/TEST_MODE

VDD48 9

48 CK_PWRGD/PD#

USB_48MHz/FSLA 10

47 VDDCPU

GND48 11

46 CPUT0

VDD96_IO 12

45 CPUC0

DOTT_96/SRCT0 13

44 GNDCPU

DOTC_96/SRCC0 14

43 CPUT1_F

GND 15

42 CPUC1_F

VDD 16

41 VDDCPU_IO

SRCT1/SE1 17

40 VOUT

SRCC1/SE2 18

39 CPUT2_ITP/SRCT8

GND 19

38 CPUC2_ITP/SRCC8

VDDPLL3_IO 20

37 VDDSRC_IO

SRCT2/SATAT 21

36 SRCT7/CR#_F

SRCC2/SATAC 22

35 SRCC7/CR#_E

GNDSRC 23

34 GNDSRC

SRCT3/CR#_C 24

33 SRCT6

SRCC3/CR#_D 25

32 SRCC6

VDDSRC_IO 26

31 VDDSRC

SRCT4 27

30 PCI_STOP#/SRCT5

SRCC4 28

29 CPU_STOP#/SRCC5

56-SSOP & TSSOP

Features/Benefits:

•

Supports spread spectrum modulation, default is 0.5%

down spread

•

Uses external 14.318MHz crystal, external crystal load

caps are required for frequency tuning

•

Selectable SRC differential push-pull pair/two single

ended outputs

Table 1: CPU Frequency Select Table

FSLC

2

B0b7

FSLB

1

B0b6

FSLA

1

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

0

0

0

266.66

0

0

1

133.33

0

1

0

200.00

0

1

1

166.66

1

0

0

333.33

1

0

1

100.00

1

1

0

400.00

1

1

1

1. FS

LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS

LC is a three-level input. Please see the VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for correct values.

Reserved

100.00

33.33 14.318 48.00 96.00