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70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

RapidWrite Mode Write Cycle

Unlike other vendors' Asynchronous Random Access Memories,

the IDT70T633/1 is capable of performing multiple back-to-back write

operations without having to pulse the R/W, CE, or BEn signals high

duringaddresstransitions. ThisRapidWriteModefunctionalityallowsthe

systemdesignertoachieveoptimumback-to-backwritecycleperformance

without the difficult task of generating narrow reset pulses every cycle,

simplifyingsystemdesignandreducingtimetomarket.

DuringthisnewRapidWriteMode,theendofthewritecycleisnow

definedbytheendingaddresstransition,insteadoftheR/WorCEorBEn

transition to the inactive state. R/W, CE, and BEn can be held active

throughout the address transition between write cycles.

CaremustbetakentostillmeettheWriteCycletime(tWC),thetimein

whichtheAddressinputsmustbestable. Inputdatasetupandholdtimes

(tDWandtDH)willnowbereferencedtotheendingaddresstransition. In

thisRapidWriteMode theI/OwillremainintheInputmodefortheduration

of the operations due to R/W being held low. All standard Write Cycle

specifications must be adhered to. However, tAS and tWR are only

applicable when switching between read and write operations. Also,

therearetwoadditionalconditionsontheAddressInputsthatmustalso

bemettoensurecorrectaddresscontrolled writes. Thesespecifications,

theAllowableAddressSkew(tAAS)andtheAddressRise/Falltime(tARF),

mustbemettousetheRapidWriteMode. Iftheseconditionsarenotmet

thereisthepotentialforinadvertentwriteoperationsatrandomintermediate

locationsasthedevicetransitionsbetweenthedesiredwriteaddresses.

5670 drw 08

tWC

tWC

tWC

tEW

tWP

tWZ

tDH

tDW

tDW

tDW

tOW

tWR

ADDRESS

CE or SEM(6)

BEn

R/

W

DATAIN

DATAOUT

(2)

(5)

(5)

tDH

tDH

(4)

Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)

NOTES:

1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and

R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.

3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.

5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).

6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.