70T6331S datasheet(21/28 Pages) RENESAS

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70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Busy Logic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

to prevent the write from proceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70T633/1 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actual write pulse can be initiated with the R/W signal. Failure to

observe this timing can result in a glitched internal write inhibit signal

and corrupted data in the slave.

Semaphores

The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18

CMOS Static RAM with an additional 8 address locations dedicated to

binarysemaphoreflags.Theseflagsalloweitherprocessorontheleftor

right sideoftheDual-PortRAMtoclaimaprivilegeovertheotherprocessor

forfunctionsdefinedbythesystemdesigner’ssoftware.Asanexample,

the semaphore can be used by one processor to inhibit the

otherfromaccessingaportionoftheDual-PortRAMoranyothershared

resource.

The Dual-Port RAM features a fast access time, with both ports

being completely independent of each other. This means that the

activity on the left port in no way slows the access time of the right port.

Both ports are identical in function to standard CMOS Static RAM and

can be read from or written to at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM. These devices have an automatic power-down

featurecontrolledbyCE0andCE1,theDual-PortRAMchipenables,and

SEM, the semaphore enable. The CE0, CE1, and SEM pins control on-

chippowerdowncircuitrythatpermitstherespectiveporttogointostandby

modewhennotselected.

Systems which can best use the IDT70T633/1 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the hardware

semaphores of the IDT70T633/1, which provide a lockout mechanism

withoutrequiringcomplexprogramming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70T633/1 does not use its semaphore

flags to control any resources through hardware, thus allowing the

systemdesignertotalflexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speedsystems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port RAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that a

shared resource is in use. If the left processor wants to use this

resource, it requests the token by setting the latch. This processor then

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70T633/1 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAMs

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT70T633/1 RAM the BUSY pin is an output if the part is used as a

master (M/S pin = VIH), and the BUSY pin is an input if the part used

as a slave (M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

split decision could result with one master indicating BUSY on one side

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for the

other part of the word.

The BUSY arbitration on a master is based on the chip enable and

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70T633/1 Dual-Port RAMs.

5670 drw 20

MASTER

Dual Port RAM

BUSYR

CE0

MASTER

Dual Port RAM

BUSYR

SLAVE

Dual Port RAM

BUSYR

SLAVE

Dual Port RAM

BUSYR

CE1

CE0

A19

BUSYL

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