FXPS7115D4 datasheet(47/72 Pages) NXP

47 / 72 page

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

The value of the 48-bit free running timer register is copied to the sensor data 0 timestamp registers each

time sensor data 0 data is latched for transmission. The timestamp is updated at the start of the sensor data 0

The timestamp register is organized to allow for optimized reading of the timestamp in I2C automatic sensor

data register read wrap-around mode as documented in Table 9.

The sensor data 0 timestamp registers are read-only registers that contain a 48-bit timestamp.

The value of the 48-bit free running timer register is copied to the sensor data 0 timestamp registers each time

sensor data 0 data is latched for transmission via SPI.

Location

Bit

Address

Symbol

66h

SNSDATA0_TIME0

SNSDATA0_TIME[7:0]

67h

SNSDATA0_TIME1

SNSDATA0_TIME[15:8]

68h

SNSDATA0_TIME2

SNSDATA0_TIME[23:16]

69h

SNSDATA0_TIME3

SNSDATA0_TIME[31:24]

6Ah

SNSDATA0_TIME4

SNSDATA0_TIME[39:32]

6Bh

SNSDATA0_TIME5

SNSDATA0_TIME[47:40]

Factory default

Access

Table 83. SNSDATA0_TIMEx - timestamp register (address 66h to 6Bh) bit allocation

7.7.20 P_MAX, P_MIN - maximum and minimum absolute pressure value registers (address

6Ch to 6Fh)

The minimum and maximum absolute pressure value registers are read-only registers that contain a sample-

by-sample continuously updated minimum and maximum 16-bit absolute pressure value. The value is reset to

0000h on a write to a DSP_CFG_U1 register that changes the value of the LPF[2:0] or ST_CTRL[3:0].

The values of P_Max and P_Min obtained during a SPI or I2C register read might not always be the same value

as the instantaneous pressure value obtained from the SNSDATA_x registers.

These registers are readable in SPI mode or I2C mode. In I2C mode, the P_xxx_H register value is latched on

a read of the P_xxx_L register value until the P_xxx_H register is read. To avoid data mismatch, the user is

always required to read the registers in sequence, P_xxx_L register first, followed by the P_xxx_H register.

Location

Bit

Address

Symbol

6Ch

P_MAX_L

P_MAX[7:0]

6Dh

P_MAX_H

P_MAX[15:8]

6Eh

P_MIN_L

P_MIN[7:0]

6Fh

P_MIN_H

P_MIN[15:8]

Factory default

Access

Table 84. P_Max and P_Min registers (address 6Ch to 6Fh) bit allocation

7.7.21 FRT - free running timer registers (addresses 78h to 7Dh)

The free running timer registers are read-only registers that contain a 48-bit free running timer. The free running

timer is clocked by the main oscillator frequency and increments every 100 ns.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.1 — 7 June 2023

47 / 72

FXPS7115D4 Datasheet(PDF) 47 Page - NXP Semiconductors

FXPS7115D4 Datasheet(HTML) 47 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL