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MB90F482 Datasheet(PDF) 53 Page - fujitsu semiconductor |
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MB90F482 Datasheet(HTML) 53 Page - fujitsu semiconductor |
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53 / 113 page  MB90480/485 Series 53 (2) Block Diagram ICCR CS4 CS3 CS2 CS1 CS0 IBSR ICCR EN BB RSC LRB TRX FBT AL Last Bit 56 7 8 24816 32 64 128 256 Sync First Byte SCL SDA IRQ IBCR IBCR SCC MSS ACK GCAA IBCR AAS GCA BER BEIE INTE INT IDAR IADR I2C enable Peripheral clock Clock selection 1 Clock dividing 1 Clock dividing 2 Clock selection 2 Shift clock generation Change timing of shift clock edge Start/stop condition detection Bus busy Repeat start Transmission/ Reception Error Arbitration lost detection Interrupt request End Start Master ACK enable GC-ACK enable Start/stop condition generatiion Slave Global call Slave address comparison |
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