6.42

709089/79S/L

High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

11

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

3. CE0 and ADS = VIL; CE1 and CNTRST = VIH.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

R/

W

ADDRESS

An

An +1

An + 2

An + 2

An + 3

An + 4

DATAIN

Dn + 2

CE0

CLK

3242 drw 11

Qn

Qn + 3

DATAOUT

CE1

tCD2

tCKHZ

tCKLZ

tCD2

tSC

tHC

tSW tHW

tSA

tHA

tCH2

tCL2

tCYC2

READ

NOP

READ

tSD tHD

(4)

(2)

(1)

(1)

tSW tHW

WRITE

(5)

R/

W

ADDRESS

An

An +1

An + 2

An + 3

An + 4

An + 5

DATAIN

Dn + 3

Dn + 2

CE0

CLK

3242 drw 12

DATAOUT

Qn

Qn + 4

CE1

OE

tCH2

tCL2

tCYC2

tCKLZ(1)

tCD2

tOHZ(1)

tCD2

tSD

tHD

READ

WRITE

READ

tSC

tHC

tSW tHW

tSA

tHA

(4)

(2)

tSW tHW