ICS9173B

VIDEO GENLOCK PLL

CLOCK SYNTHESIZER

IDT® VIDEO GENLOCK PLL

2

ICS9173B

REV D 012913

Pin Assignment

Pin Descriptions

Allowable Input Frequency to Output Frequency for ICS9173B-01 (in MHz)

(ICS9173B-15 outputs run at exactly half of the ICS9173B-01 frequencies)

FBIN

IN

GND

VDD

FS0

CLK1

OE

CLK2

1

2

3

4

8

7

6

5

8 pin SOIC

Pin Number

Pin Name

Pin Type

Pin Description

1

FBIN

Input

Feedback input.

2

IN

Input

Input for reference sync pulse.

3

GND

Power

Ground.

4

FS0

Input

Frequency select 0 input.

5

OE

Input

Output enable.

6

CLK1

Output

Clock output 1.

7

VDD

Power

Power supply (+5 V).

8

CLK2

Output

Clock output 2 (divided-by-2 from Clock 1).

fOUT for FS = 0

fOUT for FS = 1

fIN (kHz)

CLK1 Output

CLK2 Output

CLK1 Output

CLK2 Output

12 < fIN < 14 kHz

44.0 to 75

22.0 to 37.5

11.0 to 18.75

5.5 to 9.375

14 < fIN < 17 kHz

30.0 to 75

15.0 to 37.5

7.5 to 18.75

3.75 to 9.375

17 < fIN < 30 kHz

25.0 to 75

12.5 to 37.5

6.25 to 18.75

3.125 to 9.375

30 < fIN < 35 kHz

15.0 to 75

7.5 to 37.5

3.75 to 18.75

1.875 to 9.375

35 < fIN < 1000 kHz

10.0 to 75

5.0 to 37.5

2.5 to 18.75

1.25 to 9.375