AD7356 datasheet(15/18 Pages) AD

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Preliminary Technical Data

AD7356

Rev. PrC | Page 15 of 18

SERIAL INTERFACE

Figure 19 shows the detailed timing diagram for serial

interfacing to the AD7356. The serial clock provides the

conversion clock and controls the transfer of information from

the AD7356 during conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track and hold into hold mode at

which point the analog input is sampled and the bus is taken

out of three-state. The conversion is also initiated at this point

and requires a minimum of 14 SCL to complete. Once 13 SCLK

falling edges have elapsed, the track and hold will go back into

track on the next SCLK rising edge, as shown in Figure 19 at

point B. If a 16 bit data transfer is used on the AD7356, then

two trailing zeros will appear after the final LSB. On the rising

edge of CS, the conversion will be terminated and SDATAA and

SDATAB will go back into three-state. If CS is not brought high,

but is instead held low for a further 14 SCLK cycles on SDATAA,

the data from the conversion on ADCB will be output on

SDATAA.

Likewise, is CS is held low for a further 14 SCLK cycles on

SDATAA, the data from the conversion on ADCA will be output

on SDATAB. This is illustrated in Figure 20 where the case for

SDATAA is shown. In this case, the SDATA line in use will go

back into three-state on the 32nd SCLK falling edge or the rising

edge of CS, which ever occurs first.

A minimum of 14 serial clock cycles are required to perform

the conversion process and to access data from one conversion

on either data line of the AD7356. CS going low provides the

leading zero to be read in by the microcontroller or DSP. The

remaining data is then clocked out by subsequent SCLK falling

edges, beginning with a second leading zero. Thus, the first

falling clock edge on the serial clock has the leading zero

provided and also clocks out the second leading zero. The 12-bit

result then follows with the final bit in the data transfer valid on

the 14th falling edge, having being clocked out on the previous

(13th) falling edge. In applications with a slower SCLK, it may be

possible to read in data on each SCLK rising edge depending on

the SCLK frequency. The first rising edge of SCLK after the CS

falling edge would have the second leading zero provided, and

the 13th rising SCLK edge would have DB0 provided.

SCLK

DOUTA

DOUTB

2 LEADING ZEROS

THREE-

STATE

tQUIET

THREE-STATE

DB11

DB10

DB2

DB0

DB1

DB9

DB8

tACQUISITION

tCONVERT

Figure 19. Serial Interface Timing Diagram

SCLK

DOUTA

THREE-

STATE

THREE-

STATE

ZERO

DB11B

2 LEADING ZEROS

t10

DB11A

2 LEADING

ZEROS

DB10A

DB9A

ZERO

2 TRAILING ZEROS

ZERO

2 TRAILING ZEROS

Figure 20. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs

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