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STC12C5616AD Datasheet(PDF) 72 Page - STCmicro Technology Co,.Ltd

Part # STC12C5616AD
Description  Enhanced 8051 Central Processing Unit ,1T per machine cycle, faster 8~12 times than the rate of a standard 8051.
PDF  377 Pages
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Manufacturer  STC [STCmicro Technology Co,.Ltd]
Direct Link  http://www.stcmicro.com/
Logo STC - STCmicro Technology Co,.Ltd

STC12C5616AD Datasheet(HTML) 72 Page - STCmicro Technology Co,.Ltd

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P1M0 7
0
P1M1 [7 0
I/O ports Mode
00
quasi_bidirectional(standard 8051 I/O port output
,
Sink Current up to 20mA , pull-up Current is 230μA ,
Because of manufactured error, the actual pull-up current is 250uA ~ 150uA
01
push-pull output(strong pull-up output current can be up to 20mA, resistors
need to be added to restrict current
1
0
input-only (high-impedance )
11
Open Drain internal
pull-up resistors should be disabled and external
pull-up resistors need to join.
Example: MOV P1M0, #10100000B
MOV
P1M1, #11000000B
;P1.7 in Open Drain mode, P1.6 in strong push-pull output, P1.5 in high-impedance input, P1.4/P1.3/P1.2/
P1.1/P1.0 in quasi_bidirectional/weak pull-up
/weak pull-up
P1 Configure <P1.7, P1.6, P1.5, P1.4, P1.3, P1.2, P1.1, P1.0 port> (P1 address
address 90H))
P0M0 7
0
P0M1 [7 0
I/O ports Mode
00
quasi_bidirectional (standard 8051 I/O port output
,
Sink Current up to 20mA , pull-up Current is 230μA ,
Because of manufactured error, the actual pull-up current is 250uA ~ 150uA
01
push-pull output(strong pull-up output current can be up to 20mA, resistors
need to be added to restrict current
1
0
input-only (high-impedance )
11
Open Drain internal
pull-up resistors should be disabled and external
pull-up resistors need to join.
Example: MOV P0M0, #00001010B
MOV
P0M1, #00001100B
;P0.3 in Open Drain mode, P0.2 in strong push-pull output, P0.1 in high-impedance input, P0.0 in
quasi_bidirectional/weak pull-up
/weak pull-up
P0 Configure <P0.7, P0.6, P0.5, P0.4, P0.3, P0.2, P0.1, P0.0 port> (P0 address
address 80H))
Some SFRs related with I/O ports are listed below.
P3 register (bit addressable
SFR name Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
P3
B0H
name
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P3 register could be bit-addressable and set/cleared by CPU. And P3.7~P3.0 coulde be set/cleared by CPU.
P3M0 register (non bit addressable
SFR name Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
P3M0
B1H
name P3M0.7 P3M0.6 P3M0.5 P3M0.4 P3M0.3 P3M0.2 P3M0.1 P3M0.0
P3M1 register (non bit addressable
SFR name Address
bit
B7
B6
B5
B4
B3
B2
B1
B0
P3M1
B2H
name P3M1.7 P3M1.6 P3M1.5 P3M1.4 P3M1.3 P3M1.2 P3M1.1 P3M1.0
72



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