F-240 datasheet(21/55 Pages) ETC2

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Swissbit AG

Swissbit reserves the right to change products or specifications without notice.

Revision: 0.90

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F-240_data_sheet_CA-HxBV_Rev090

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Page 21 of 55



Bit 2 shall be set to 1 indicating that word 88 is valid and reflects the supported UDMA

6.7.14 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track

These fields contain the current number of user addressable Cylinders, Heads, and Sectors/Track in the current

translation mode.

6.7.15 Word 57-58: Current Capacity

This field contains the product of the current cylinders, heads and sectors.

6.7.16 Word 59: Multiple Sector Setting



Bits 15-9 are reserved and must be set to ‘0’.



Bit 8 is set to ‘1’, to indicate that the Multiple Sector Setting is valid.



Bits 7:0 are the current setting for the number of sectors to be transferred for every interrupt, on

Read/Write Multiple commands; the only values returned are ‘00h’ or ‘01h’.

6.7.17 Word 60-61: Total Sectors Addressable in LBA Mode

This field contains the number of sectors addressable for the Drive in LBA mode only.

6.7.18 Word 63: Multi-Word DMA transfer

Bits 15 through 8 of word 63 of the Identify Device parameter information is defined as the Multiword DMA mode

selected field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Only one

of bits may be set to one in this field by the drive to indicate the multiword DMA mode which is currently

selected.

Of these bits, bits 15 through 11 are reserved. Bit 8, if set to one, indicates that Multiword DMA mode 0 has been

selected. Bit 9, if set to one, indicates that Multiword DMA mode 1 has been selected. Bit 10, if set to one,

indicates that Multiword DMA mode 2 has been selected.

Selection of Multiword DMA modes 3 and above are specific to Drive are as described in Word 163.

Bits 7 through 0 of word 63 of the Identify Device parameter information is defined as the Multiword DMA data

transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.

Any number of bits may be set to one in this field by the drive to indicate the Multiword DMA modes it is

capable of supporting.

Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the drive supports Multiword DMA

mode 0. Bit 1, if set to one, indicates that the drive supports Multiword DMA modes 1 and 0. Bit 2, if set to one,

indicates that the Drive supports Multiword DMA modes 2, 1 and 0.

Support for Multiword DMA modes 3 and above are specific to Drive are reported in word 163 as described in

Word 163.

6.7.19 Word 64: Advanced PIO transfer modes supported

This field is bit significant. Any number of bits may be set to ‘1’ in this field by the drive to indicate the

advanced PIO modes it is capable of supporting.



Bits 7-2 are reserved for future advanced PIO modes.



Bit 1 is set to ‘1’, indicates that the Drive supports PIO mode 4.



Bit 0 is set to ‘1’ to indicate that the Drive supports PIO mode 3.

Support for PIO modes 5 and above are specific to Drive are reported in word 163 as described in Word 163.

6.7.20 Word 65: Minimum Multi-Word DMA transfer cycle time

Word 65 of the parameter information of the Identify Device command is defined as the minimum Multiword

DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host,

the Drive guarantees data integrity during the transfer.

If this field is supported, bit 1 of word 53 shall be set to one. The value in word 65 shall not be less than the

minimum cycle time for the fastest DMA mode supported by the device. This field shall be supported by all

Drives supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this field is not supported, the

Drive shall return a value of zero in this field.

6.7.21 Word 66: Recommended Multi-Word DMA transfer cycle time

Word 66 of the parameter information of the Identify Device command is defined as the recommended

Multiword DMA transfer cycle time. This field defines, in nanoseconds, the cycle time that, if used by the host,

may optimize the data transfer from by reducing the probability that the Drive will need to negate the DMARQ

signal during the transfer of a sector.

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