ICS841484I Data Sheet

FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR

ICS841484DKI REVISION A NOVEMBER 7, 2012

5

©2012 Integrated Device Technology, Inc.

Table 5. Crystal Characteristics

NOTE: Characterized using an 18pF parallel resonant crystal.

AC Electrical Characteristics

Table 6A. PCI Express Jitter Specifications, VDD = 3.3V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.

NOTE: PCIe jitter parameters were obtained with Spread Spectum Modulation disabled.

NOTE: PCIe Gen 2 and Gen 3 jitter parameters were obtained with REF_OUT disabled.

NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1

is 86ps peak-to-peak for a sample size of 106 clock periods.

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS

(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).

NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express

Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.

NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Fundamental

Frequency

25

MHz

Equivalent Series Resistance (ESR)

50



Shunt Capacitance

7pF

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

PCIe Industry

Specification

Units

tj

(PCIe Gen 1)

Phase Jitter

Peak to Peak

Note 1, 4

100MHz, 25MHz crystal input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

14.2

30.6

86

ps

tREFCLK_HF_RMS

(PCIe Gen 2)

Phase Jitter

RMS; NOTE 2, 4

100MHz, 25MHz crystal input

High Band: 1.5MHz - Nyquist

(clock frequency/2)

0.77

1.4

3.1

ps

tREFCLK_LF_RMS

(PCIe Gen 2)

Phase Jitter

RMS; NOTE 2, 4

100MHz, 25MHz crystal input

Low Band: 10kHz - 1.5MHz

0.17

0.45

3.0

ps

tREFCLK_LF_RMS

(PCIe Gen 3)

Phase Jitter

RMS; NOTE 3, 4

100MHz, 25MHz crystal input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

0.16

0.35

0.8

ps