ICS843241 datasheet(10/19 Pages) RENESAS

10 / 19 page

IDT™ / ICS™ SAS/SATA CLOCK GENERATOR

ICS843241BG REV. A AUGUST 20, 2008

ICS843241

FEMTOCLOCKS™ SAS/SATA CLOCK GENERATOR

TERMINATION FOR 3.3V LVPECL OUTPUTS

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are rec-

ommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

FIGURE 3B. LVPECL OUTPUT TERMINATION

FIGURE 3A. LVPECL OUTPUT TERMINATION

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal dis-

tortion.

Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts

may exist and it would be recommended that the board design-

ers simulate to guarantee compatibility across all printed circuit

and clock component process variations.

CC - 2V

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

o = 50Ω

FOUT

FIN

INPUTS:

LVCMOS CONTROL PINS

All control pins have internal pulldowns; additional resistance is

not required but can be added for additional protection. A 1k

resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT PINS

ICS843241 Datasheet(PDF) 10 Page - Renesas Technology Corp