ICS843404 datasheet(14/20 Pages) RENESAS

14 / 20 page

843404AG

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 17, 2005

Integrated

Circuit

Systems, Inc.

ICS843404

LVCMOS/CRYSTAL-TO-3.3V LVPECL AND

LVDS CLOCK GENERATOR

LAYOUT GUIDELINE

Figure 6 shows a schematic example of the ICS843404. An

example of LVEPCL termination is shown in this schematic.

Additional LVPECL termination approaches are shown in the

LVPECL Termination Application Note. In this example, an

FIGURE 6. ICS843404 SCHEMATIC EXAMPLE

18pF parallel resonant 25.5MHz crystal is used. The C1=27pF

and C2=33pF are recommended for frequency accuracy. For

different board layout, the C1 and C2 may be slightly ad-

justed for optimizing frequency accuracy.

18pF

0.1u

25.5 MHz

VDD

Zo = 50

VDDO

(U1,26)

0.1u

ICS843404

VCO_SEL

VDDO_LVDS

LVDS0

nLVDS0

LVDS1

nLVDS1

LVPECL_FSELB0

LVPECL_FSELB1

VDDA

LVPECL_FSELA0

VDD

LVPECL_FSELA1

XTAL_OUT

XTAL_IN

GND

TEST_CLK

nLVPECLA0

LVPECLB0

nLVPECLB0

XTAL_SEL

LVPECLA0

VDDO_LVPECL

LVDS_FSEL1

LVDS_FSEL0

0.1u

VDD = 3.3V

Zo = 50

10u

0.1u

100

Zo = 50

(U1,3)

22pF

VDDO

VDDO = 3.3V

ICS843404

LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR

TSD

IDT™ / ICS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR

ICS843404

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