ICS87004AGI REVISION D JANUARY 4, 2010

14

©2009 Integrated Device Technology, Inc.

ICS87004I Data Sheet

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Revision History Sheet

Rev

Table

Page

Description of Change

Date

B

T5A

T5B

6

6

9

AC Characteristics Table - corrected Static Phase Offset limits from

-75ps min/50ps typical/175ps max. to 025ps min./100ps typical/225ps max.

AC Characteristics Table - corrected Static Phase Offset limits from -25ps typical to

-50ps typical.

Added ""Recommendations for Unused Input and Output Pins"".

7/25/05

C

T5A

T5B

6

6

AC Characteristics Table - corrected Static Phase Offset limits from -25ps min/

100ps typical/225ps max. to -100ps min/50ps typical/200ps max.

Corrected Output Skew limits from 50ps max. to 65ps max.

Corrected Propagation Delay limits from 6.1ns max. to 6.2ns max.

AC Characteristics Table - corrected Static Phase Offset limits from -225ps min./

50ps typical/125ps max. to -250ps min./-25ps typical/150ps max.

Corrected Output Skew limits from 45ps max. to 65ps max.

Corrected Propagation Delay limits from 6.7ns max. to 6.9ns max.

10/14/05

C

T8

14

Ordering Information Table - added Lead-Free marking.

12/7/07

D

T4D

T5A, T5B

T8

6

7

11

13

Differential DC Characteristics Table - updated NOTES 1, 2.

AC Characteristics Tables - Static Phase Offset, split CLKx into 2 rows. Specs changed for

CLK1/nCLK1. Added Thermal note.

Updated Differential Clock Input Interface section.

Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.

Converted datasheet format.

12/7/09