OPA863DBVR datasheet(22/52 Pages) TI

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8.3 Feature Description

8.3.1 Input Stage

The OPAx863 include a rail-to-rail input stage. The main stage differential pair using PNP bipolar transistors

operates for common-mode input voltages from VS– – 0.2 V to VS+ – 1.6 V. The amplifier inputs transition into

the auxiliary stage using NPN transistors for common-mode input voltages from VS+ – 1.6 V till VS+ + 0.2 V. The

PNP and NPN input stages offer a gain-bandwidth product of 50 MHz and a voltage noise density of 6.3 nV/√Hz.

The offset voltage for the two input stages is matched to lie within the device specifications. The auxiliary NPN

input stage does not use the slew-boost circuit during large-signal transient response. The input bias current for

the PNP and NPN input stages is opposite in polarity, which adds an additional offset based on the values of

the gain-setting and feedback resistors. A common-mode input voltage transition between these input stages

causes a crossover distortion that must be considered in high-frequency applications requiring excellent linearity.

Limit the common-mode input voltage to VS+ – 1.6 V (maximum) for main-stage operation across process and

ambient temperature.

The OPAx863 are bipolar amplifiers; therefore, the two inputs are protected with antiparallel back-to-back diodes

between the inputs, which limits the maximum input differential voltage to 1 V. The amplifier is slew limited,

and the two inputs are pulled apart up to 1 V when the antiparallel diodes begin to conduct in very fast input

or output transient conditions. Make sure to use gain-setting and feedback resistors large enough to limit the

current through these diodes in such conditions.

8.3.2 Output Stage

The OPAx863 feature a rail-to-rail output stage with possible signal swing from VS– + 0.2 V to VS+ – 0.2 V.

Violating the output headroom of either supply causes output signal clipping and introduces distortion.

The OPAx863 integrate an output short-circuit protection circuit that makes the device rugged for use in real-

world applications.

8.3.2.1 Overload Power Limit

The OPAx863 include overload power limiting that limits the increase in device quiescent current with output

saturated to either of the supplies. Typically, when an amplifier output saturates, the two inputs are pulled

apart, which can enable the slew-boost circuit. The input differential voltage is an error voltage in negative

feedback that the amplifier core nullifies by engaging the slew-boost circuit and driving the output stage deeper

into saturation. After the input to an amplifier attains a value large enough to saturate the output, any further

increase in this input excitation results in a finite input differential voltage. As the output stage transistor is

pushed deeper into saturation, the base-to-collector current gain (hFE) drops with an increase in the base and

collector current, and an increase in the device quiescent current. This increase in quiescent current can cause

a catastrophic failure in multichannel, high-gain, high-density front-end designs, and reduce operating lifetime in

portable, battery-powered systems.

The OPAx863 overload power limiting includes an intelligent output saturation-detection circuit that limits the

device quiescent current to 2.2-mA per channel under dc overload conditions. This increase in quiescent current

is smaller with ac input or output and output saturation duration for only a fraction of the overall signal time

period. Table 8-1 compares the increase in quiescent current with 50

‑mV input overdrive for OPAx863 devices

and other voltage-feedback amplifiers without overload power limit.

Table 8-1. Quiescent Current With Saturated Outputs

DEVICE

INPUT DIFFERENTIAL

VOLTAGE

QUIESCENT CURRENT

DURING OVERLOAD

INCREASE IN IQ

FROM STEADY-STATE

CONDITION

OPAx863 with overload power limit

50 mV

1.1 mA

1.57 ×

Competitor amplifier without overload power limit

50 mV

1.96 mA

3.43 ×

OPA863, OPA2863, OPA4863

SBOS982J – JUNE 2020 – REVISED JUNE 2023

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