IDTTM

Progammable Timing Control HubTM for Next Gen P4TM Processor

701J—01/25/10

ICS952601

Programmable Timing Control HubTM for Next Gen P4TM Processor

14

The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to

be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the

PCI_STOP register bit.

PCI Stop Functionality

#

P

O

T

S

_

I

C

PU

P

C#

U

P

CC

R

S#

C

R

S6

6

V

3I

C

P

/

F

I

C

PT

O

D

/

B

S

UF

E

Re

t

o

N

1l

a

m

r

o

Nl

a

m

r

o

Nl

a

m

r

o

Nl

a

m

r

o

Nz

H

M

6

6z

H

M

3

3z

H

M

8

4z

H

M

8

1

3

.

4

1

0l

a

m

r

o

Nl

a

m

r

o

N6

*

f

e

r

I

t

a

o

l

F

r

o

w

o

Lz

H

M

6

6w

o

Lz

H

M

8

4z

H

M

8

1

3

.

4

1

The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all

PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,

the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and

the SRC# will latch low as shown below.

PCI_STOP#

Tsu

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# Assertion (transition from '1' to '0')

The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After

detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free

manner.

PCI_STOP#

Tsu

Tdrive_SRC

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# - De-assertion