IDTTM

Progammable Timing Control HubTM for Next Gen P4TM Processor

701J—01/25/10

ICS952601

Programmable Timing Control HubTM for Next Gen P4TM Processor

18

To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or

tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during

PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the

corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",

"SRC_Stop" and "PwrDwn" register bit settings.

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Notes:

1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"

2. Iref x 6 and Iref x 2 is the output current in the corresponding mode

3. See Control Registers section for bit address

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Notes:

1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"

2. Iref x 6 and Iref x 2 is the output current in the corresponding mode

3. See Control Registers section for bit address

Differential Clock Tristate