10

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)

— ENDIAN SELECTION

Thisisadualpurposepin.AtthetimeofReset,theBEselectfunctionisactive,

permittingachoiceofBig-orLittle-Endianbytearrangementfordatareadfrom

PortB.Thisselectiondeterminestheorderbywhichbytes(orwords)ofdata

aretransferredthroughthisport.Forthefollowingillustrations,assumethata

byte (or word) bus size has been selected for Port B. (Note that when Port B

isconfiguredforalongwordsize,theBig-Endianfunctionhasnoapplication

and the BE input is a “don’t care”1.)

AHIGHontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW

toHIGHwillselectaBig-Endianarrangement.Inthiscase,themostsignificant

byte (word) of the long word written to Port A will be read from Port B first; the

leastsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom

PortBlast.

ALOWontheBE/FWFTinputwhentheReset(RS1)inputgoesfromLOW

toHIGHwillselectaLittle-Endianarrangement.Inthiscase,theleastsignificant

byte (word) of the long word written to Port A will be read from Port B first; the

mostsignificantbyte(word)ofthelongwordwrittentoPortAwillbereadfrom

Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure

3 (Reset) for an Endian select timing diagram.

— TIMING MODE SELECTION

AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween

two possible timing modes: IDT Standard mode or First Word Fall Through

(FWFT)mode.OncetheReset(RS1)inputisHIGH,aHIGHontheBE/FWFT

inputduringthenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectIDT

Standard mode. This mode uses the Empty Flag function (EF) to indicate

whether or not there are any words present in the FIFO memory. It uses the

FullFlagfunction(FF)toindicatewhetherornottheFIFOmemoryhasanyfree

space for writing. In IDT Standard mode, every word read from the FIFO,

includingthefirst,mustberequestedusingaformalreadoperation.

OncetheReset(RS1)inputisHIGH,aLOWontheBE/FWFTinputduring

thenextLOW-to-HIGHtransitionofCLKAandCLKBwillselectFWFTmode.

ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere

isvaliddataatthedataoutputs(B0-B35).ItalsousestheInputReadyfunction

(IR)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.

IntheFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata

outputs,noreadrequestnecessary.Subsequentwordsmustbeaccessedby

performingaformalreadoperation.

Following Reset, the level applied to the BE/FWFT input to choose the

desiredtimingmodemustremainstaticthroughoutFIFOoperation.Referto

Figure 3 (Reset) for a First Word Fall Through select timing diagram.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

TworegistersintheIDT723663/723673areusedtoholdtheoffsetvalues

fortheAlmost-EmptyandAlmost-Fullflags.TheAlmost-Emptyflag(AE)Offset

registerislabeledXandAlmost-Fullflag(AF)OffsetregisterislabeledY.The

offsetregisterscanbeloadedwithpresetvaluesduringtheresetoftheFIFO,

programmed in parallel using the FIFO’s Port A data inputs, or programmed

inserialusingtheSerialData(SD)input(seeTable1).FS2FS0/SD,andFS1/

SEN function the same way in both IDT Standard and FWFT modes.

SIGNAL DESCRIPTION

RESET (RS1, RS2)

After power up, a Reset operation must be performed by providing a LOW

pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the

IDT723663/723673undergoesacompleteresetbytakingitsReset(RS1and

RS2)inputLOWforatleastfourPortAclock(CLKA)andfourPortBclock(CLKB)

LOW-to-HIGHtransitions.TheResetinputscanswitchasynchronouslytothe

clocks.AResetinitializestheinternalreadandwritepointersandforcestheFull/

Input Ready flag (FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW,

theAlmost-Emptyflag(AE)LOW,andtheAlmost-Fullflag(AF)HIGH.AReset

(RS1)alsoforcestheMailboxflag(MBF1)oftheparallelmailboxregisterHIGH,

and at the same time the RS2 and MBF2 operate likewise. After a Reset, the

FIFO’s Full/Input Ready flag is set HIGH after two write clock cycles to begin

normaloperation.

ALOW-to-HIGHtransitionontheFlFOReset(RS1)inputlatchesthevalue

of the Big-Endian (BE) input for determining the order by which bytes are

transferredthroughPortB.

A LOW-to-HIGH transition on the FlFO Reset (RS1) input also latches the

valuesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-

FullandAlmost-Emptyoffsetprogrammingmethod(fordetailsseeTable1,Flag

Programming, and Almost-Empty and Almost-Full flag offset programming

section). The relevant Reset timing diagram can be found in Figure 3.

PARTIAL RESET (PRS)

TheFIFOmemoryoftheIDT723663/723673undergoesalimitedresetby

taking its Partial Reset (PRS) input LOW for at least four Port A clock (CLKA)

andfourPortBclock(CLKB)LOW-to-HIGHtransitions.TheRTMpinmustbe

LOW during the time of Partial Reset. The Partial Reset input can switch

asynchronouslytotheclocks.APartialResetinitializestheinternalreadand

write pointers and forces the Full/Input Ready flag (FF/IR) LOW, the Empty/

Output Ready flag (EF/OR) LOW, the Almost-Empty flag (AE)LOW,andthe

Almost-Fullflag(AF)HIGH.APartialResetalsoforcestheMailboxflag(MBF1,

MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,theFIFO’s

Full/InputReadyflagissetHIGHaftertwoWriteClockcyclestobeginnormal

operation. See Figure 4, Partial Reset (IDT Standard and FWFT Modes) for

therelevanttimingdiagram.

Whateverflagoffsets,programmingmethod(parallelorserial),andtiming

mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial

Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof

the reset operation. A Partial Reset may be useful in the case where

reprogramming a FIFO following a Reset would be inconvenient.

RETRANSMIT (RT)

The FIFO memory of these devices undergoes a Retransmit by taking its

associatedRetransmit(RT)inputLOWforatleastfourPortAClock(CLKA)and

fourPortBClock(CLKB)LOW-to-HIGHtransitions.TheRetransmitinitializes

the read pointer of FIFO to the first memory location.

TheRTMpinmustbeHIGHduringthetimeofRetransmit.NotethattheRT

inputismuxedwiththePRSinput,thestateoftheRTMpindeterminingwhether

thispinperformsaRetransmitoraPartialReset.SeeFigure19forRetransmit

(Standard IDT mode) and Figure 20 for Retransmit (FWFT mode) timing

diagrams.

NOTE:

1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with

unused inputs) must not be left open, rather they must be either HIGH or LOW.