24

COMMERCIALTEMPERATURERANGE

IDT723663/723673 CMOS SyncFIFOTM WITH BUS-MATCHING

4,096 x 36 x 2 and 8,192 x 36 x 2

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and

rising CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.

2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.

Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and

rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.

2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.

3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.

Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).

CSB

EF

W/RB

MBB

ENB

B0-B35

CLKB

FF

CLKA

CSA

5610 drw16

W/

RA

A0-A35

MBA

ENA

12

tCLK

tCLKH

tCLKL

tENS2

tENH

tA

tSKEW1

tCLK

tCLKL

tENS2

tENS2

tDS

tENH

tENH

tDH

To FIFO

Previous Word in FIFO Output Register

Next Word From FIFO

LOW

HIGH

LOW

HIGH

LOW

HIGH

(1)

FIFO Full

WFF

WFF

t

t

tCLKH

AE

CLKA

ENB

5610 drw17

ENA

CLKB

2

1

tENS2

tENH

tSKEW2

tPAE

tPAE

tENS2

tENH

X Words in FIFO

(X+1) Words in FIFO

(1)