80KSW0005 datasheet(44/50 Pages) RENESAS

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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

20 Pin Summary

Pin Name

Function

Supply

Interface

Pin Function Description

ADS

I2C(VDD, GND)

CMOS Input

I2C address width select. Set ADS = GND for 7-bit CPS-10Q slave address.

ADS = Vdd for 10-bit. NOTE: SUPPLY / LEVELS REQUIREMENTS ARE UNIQUE

FROM THE OTHER I2C PINS.

DNC

Do Not Connect. This pin should be left FLOATING. It should not be connected to any

other signal or power rail.

GND

Digital Ground

(CMOS)

Digital GND. All pins must be tied to single potential power supply ground plane.

GNDS

Analog Ground

(CMOS)

Analog GND. All pins must be tied to single potential ground supply plane.

ID0 - ID9

I2C(VDD, GND)

CMOS Input

I2C Slave ID addresses. This should be set statically to Vdd or GND at power-up.

NOTE: SUPPLY / LEVELS REQUIREMENTS ARE UNQUE FROM THE OTHER I2C

PINS.

I2C(VDD, GND)

CMOS Input

Select the I2C Master or Slave mode. Logic high for Master mode

IRQ

Interrupt

(VDD3, GND)

CMOS Open

Drain Output

This is interrupt output pin whose value is given by the Error Management Block. Note:

This is an open drain and requires an external pull-up resistor.

REF_CLK +/- SERDES Clock

(VDD, GND)

CML Differential

Input

This clock is used as the 156.25 MHz reference for standard SERDES operation.

REXTN,

REXTP

Rext

External bias resistor. Rextn must be connected to Rextp with a 12k Ohm resistor. This

establishes the drive bias on the SERDES output. This provides CML driver stability

across process and temperature.

RST

Reset

(VDD3, GND)

CMOS Input

Global Reset. Sets all internal registers to default values. Resets all PLLs. Resets all

port configurations. This is a HARD Reset.

RX0+/- to

RX39+/-

sRIO Receive

(VDDS, GNDS)

RIO Differential

Input

Differential receiver inputs, Lanes 0 to 39

SCL

I2C(VDD3, GND)

CMOS Input

I2C Clock.

SDA

I2C(VDD3, GND)

CMOS IO

I2C Serial Data IO. Data direction is determined by the I2C Read/Write bit. See I2C sec-

tion for further detail.

SPD[1:0]

SPD

(VDD, GND)

CMOS Input

Speed Select Pins. These pins define sRIO port speed at RESET for all ports. The

RESET setting may be overridden by subsequent programming of the QUAD_CTRL

pins must remain STATICALLY BIASED after power-up.

TCK

JTAG

(VDD3, GND)

CMOS Input

JTAG Tap Port Clock

TDI

JTAG

(VDD3, GND)

CMOS Input

JTAG Tap Port Input

TDO

JTAG

(VDD3, GND)

CMOS output

JTAG Tap Port Output

TMS

JTAG

(VDD3, GND)

CMOS Input

JTAG Tap Port Mode Select

TRST

JTAG

(VDD3, GND)

CMOS Input

JTAG Tap Port Asynchronous Reset

TX0+/- to

TX39+/-

sRIO Transmit

(VDDS, GNDS)

RIO Differential

Output

Differential transmitter outputs, Lanes 0 to 39

VDD

1.2V Digital

Power (CMOS)

Digital VDD. All pins must be tied to single potential power supply plane.

VDD3

3.3V Digital

Power (CMOS)

Digital Interface VDD. All pins must be tied to single potential power supply plane.

Table 39 Pin Summary (Alphabetical)

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